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7 udc endpoint 0 control/status register, 1 out packet ready (opr), 2 in packet ready (ipr) – Intel STRONGARM SA-1100 User Manual

Page 218: 3 sent stall (sst), 4 force stall (fst), 5 data end (de), 6 setup end (se), 7 serviced opr (so), 7 udc endpoint 0 control/status register -68

7 udc endpoint 0 control/status register, 1 out packet ready (opr), 2 in packet ready (ipr) | 3 sent stall (sst), 4 force stall (fst), 5 data end (de), 6 setup end (se), 7 serviced opr (so), 7 udc endpoint 0 control/status register -68 | Intel STRONGARM SA-1100 User Manual | Page 218 / 388 7 udc endpoint 0 control/status register, 1 out packet ready (opr), 2 in packet ready (ipr) | 3 sent stall (sst), 4 force stall (fst), 5 data end (de), 6 setup end (se), 7 serviced opr (so), 7 udc endpoint 0 control/status register -68 | Intel STRONGARM SA-1100 User Manual | Page 218 / 388