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3 udc control register, 1 udc disable (udd), 2 udc active (uda) – Intel STRONGARM SA-1100 User Manual

Page 214: 3 bit 2 reserved, 4 endpoint 0 interrupt mask (eim), 5 receive interrupt mask (rim), 6 transmit interrupt mask (tim), 4control field -80

3 udc control register, 1 udc disable (udd), 2 udc active (uda) | 3 bit 2 reserved, 4 endpoint 0 interrupt mask (eim), 5 receive interrupt mask (rim), 6 transmit interrupt mask (tim), 4control field -80 | Intel STRONGARM SA-1100 User Manual | Page 214 / 388 3 udc control register, 1 udc disable (udd), 2 udc active (uda) | 3 bit 2 reserved, 4 endpoint 0 interrupt mask (eim), 5 receive interrupt mask (rim), 6 transmit interrupt mask (tim), 4control field -80 | Intel STRONGARM SA-1100 User Manual | Page 214 / 388
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