Zilog Z16C35 - Manual (Page 98)

ISCC
User Manual
UM011002-0808
92
Bit combination 10 is the Reset Transmit CRC Generator Command
This command initializes the CRC generator. It is usually issued in the initialization rou-
tine and after the CRC has been transmitted. A Channel Reset will not initialize the gener-
ator and this command should not be issued until after the transmitter has been enabled in
the initialization routine.
Bit combination 11 is the Reset Transmit Under-run/EOM Latch Command
This command controls the transmission of CRC at the end of transmission (EOM). If this
latch has been reset, and a transmit underrun occurs, the SCC cell automatically appends
CRC to the message. In SDLC mode with Abort on Underrun selected, the SCC cell sends
an abort, and Flag on underrun if the TX Underrun/EOM latch has been reset.
At the start of the CRC transmission, the Tx Underrun/EOM latch is set. The Reset com-
mand can be issued at any time during a message. If the transmitter is disabled, this com-
mand will not reset the latch. However, if no External Status interrupt is pending, or if a
Reset External Status interrupt command accompanies this command while the transmitter
is disabled, an External/Status interrupt is generated with the Tx Underrun/EOM bit reset
in RR0.
Bits D5-D3 are the Command Codes for the SCC Cell.
Bit combination 000 is a Null Command.
The Null command has no effect on the SCC.
Bit combination 001 is the Point High Command
This command effectively adds eight to the Register Pointer (D2-D0) by allowing WR8
through WR15 to be accessed. The Point High command and the Register Pointer bits are
written simultaneously. This command is used when the ISCC is configured to be in the
non-multiplexed bus mode. Note that WR0 changes form depending upon the bus mode
selection.
Bit combination 010 is the Reset External/Status Interrupts Command
After an External/Status interrupt (a change on a modem line or a break condition, for
example), the status bits in RR0 are latched. This command re-enables the bits and allows
interrupts to occur again as a result of a status change. Latching the status bits captures
short pulses until the CPU has time to read the change.
The SCC cell contains simple queueing logic associated with most of the external status
bits in RR0. If another External/Status condition changes while a previous condition is
still pending (Reset External/Status Interrupts has not yet been issued) and this condition
persists until after the command is issued, this second change causes another External/Sta-
tus interrupt. However, if this second status change does not persist (there are two transi-
tions), another interrupt is not generated. Exceptions to this rule are detailed in the RR0
description.
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