Zilog Z16C35 - Manual (Page 28)

ISCC
User Manual
UM011002-0808
22
2.4.3 SCC Cell Register Reset
Table 2-5 lists the contents of the SCC cell registers after a hardware reset and after a
channel reset.
Table 2–5. SCC Cell Reset Value
2.4.4 DMA Cell Registers
The DMA cell contains seventeen registers counting the Bus Configuration Register. All
of these registers are read/write exept the Bus Configuration Register (write only), the
Channel Command Address Register (write only), the DMA Status Register (read only),
the Interrupt Command Register (write only), and the Interrupt Status Register (read only).
The reset content of all of the DMA registers identified in the address map is all zeroes.
2.4.5 DMA Register Access, Multiplexed Bus
The registers in the ISCC in the multiplexed bus mode are addressed via the address on
AD7-AD0 which is latched by the rising edge of /AS.
2
Register Hardware Reset Channel Reset
WR0 00000000 00000000
WR1 00x00x00 00x00x00
WR2 xxxxxxxx xxxxxxxx
WR3 xxxxxxx0 xxxxxxx0
WR4 xxxxx1xx xxxxx1xx
WR5 0xx0000x 0xx0000x
WR6 xxxxxxxx xxxxxxxx
WR7 xxxxxxxx xxxxxxxx
WR9 110000xx xx0xxxxx
WR10 00000000 0xx00000
WR11 00001000 xxxxxxxx
WR12 xxxxxxxx xxxxxxxx
WR13 xxxxxxxx xxxxxxxx
WR14 xx100000 xx1000xx
WR15 11111000 11111000
RR0 01xxx100 01xxx100
RR1 00000110 00000110
RR3 00000000 00000000
RR10 00000000 00000000
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