Zilog Z16C35 - Manual (Page 32)

ISCC
User Manual
UM011002-0808
26
Chapter 3 ISCC™ DMA and Ancillary
Support Circuitry
3.1 INTRODUCTION
The most important feature of the ISCC other than SCC cell is the integrated, four channel
DMA controller. As in the original SCC, the serial channels of the ISCC are supported by
ancillary circuitry for generating clocks and performing data encoding and decoding. This
chapter presents a description of these functional blocks.
3.2 DMA
The ISCC™ contains four independent DMA Channels, one for each receiver and trans-
mitter. The DMA channels operate in fly-by mode; a 32-bit transfer address is generated
along with the bus acquisition signals for executing the DMA transfer. Each DMA con-
sists of a 32-bit address counter, a 16-bit (transfer) counter, and the required sequencing
and control circuitry.
The DMA is set up by initializing the address resisters with the starting address of the
DMA transfer and the count registers for the length of the block. Following this, the option
to increment or decrement the address after a transfer is selected. Other DMA selections
that must be programmed include the DMA priority, if separate bus requests are to be
made for each DMA channel, the programming of the interrupt vector and the option to
include interrupt status in the vector. Note that a no vector interrupt option is also possible.
Following this, the Interrupt On Abort is programmed as desired, the individual channel
interrupt enables are programmed, the Master Interrupt Enable is set (if interrupts are
used), and lastly the appropriate DMA channels are enabled.
3.2.1 Receiver DMA Operation
Assuming the receiver has been appropriately set up, the DMA request will be made when
the receive FIFO contains a byte and will continue to hold the bus and transfer bytes until
the FIFO is empty. Once started, the DMA for the channel continues until the FIFO is
empty even though a request from a higher priority DMA channel arises. Upon comple-
tion of the current DMA channel service, the next highest priority DMA channel com-
mences its operation. The ISCC continues to hold the bus until all pending DMA requests
have been served. Note that if the Bus Request Per Channel option has been selected, then
the bus will be released and subsequently re-requested for each channel. At the completion
of the block transfer (terminal count reached), an interrupt will be generated, if enabled. If
selected, the interrupt vector will indicate the interrupt source according to Table 3-1.
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