Zilog Z16C35 - Manual (Page 20)

ISCC
User Manual
UM011002-0808
14
In the DMA Read with Byte Swap enabled:
In this table DMA read refers to a DMA controlled transfer from memory to the ISCC and
DMA write refers to a DMA controlled transfer from the ISCC to memory. Read refers to
a normal peripheral transaction where the CPU reads data from the ISCC and Write refers
to a normal peripheral transaction where the CPU writes data to the ISCC.
2.3 I/O INTERFACE CAPABILITIES
The ISCC offers the choice of Polling, Interrupt (vectored or non-vectored), and DMA
Transfer modes to transfer data, status, and control information to and from the CPU.
2.3.1 Polling
In this mode all interrupts and the DMA’s are disabled. Three status registers in the SCC
are automatically updated whenever any function is performed. For example, end-of-
frame in SDLC mode sets a bit in one of these status registers. With polling, the CPU must
periodically read a status register until the register contents indicate the need for some
CPU action to be taken. Only one register in the SCC cell needs to be read; depending on
Table 2–1. ISCC Bus Access Summary
Process
Byte
Enable Swap
Select
Lower 8 Bits Action on Bus Upper 8 Bits
Read X X data same data
Write X X data read data ignored
DMA Write 0 X data same data
DMA Read 0 X data read data ignored
DMA Write 1 X data same data
DMA Read 1 0 depends upon A0
(see below)
Byte Swap Select A0 ISCC Accepts Data
0 0 Upper 8 Bits of Bus
0 1 Lower 8 Bits of Bus
1 0 Lower 8 Bits of Bus
1 1 Upper 8 Bits of Bus
Page 14 of 316