Zilog Z16C35 - Manual (Page 119)

ISCC
User Manual
UM011002-0808
113
plexer just before the internal receive clock input. A hardware reset forces the receive
clock to come from the /RTxC pin.
Bits 4 and 3 are the Transmit Clock select bits 1 and 0
These bits determine the source of the transmit clock as shown in Table 5-10. They do not
interfere with any of the modes of operation of the ISCC, but simply control a multiplexer
just before the internal transmit clock input. The DPLL output that may be used to feed the
transmitter in FM modes lags by 90 degrees the output of the DPLL used by the receiver.
This makes the received and transmitted bit cells occur simultaneously, neglecting delays.
A hardware reset selects the /TRxC pin as the source of the transmit clocks.
Bit 2 is the TRxC Pin O//I control bit
This bit determines the direction of the /TRxC pin. If this bit is set to “1,” the TRxC pin is
an output and carries the signal selected by D1 and D0 of this register. However, if either
the receive or the transmit clock is programmed to come from the /TRxC pin, /TRxC will
be an input, regardless of the state of this bit. The /TRxC pin is also an input if this bit is
set to “0” A hardware reset forces this bit to “0.”
Bits 1 and 0 are the /TRxC Output Source select bits 1 and 0
These bits determine the signal to be echoed out of the ISCC via the /TRxC pin as given in
Table 5-11. No signal is produced if /TRxC has been programmed as the source of either
the receive or the transmit clock. If TRxC O//I (bit 2) is set to “0,” these bits are ignored.
Table 5–31. Receive Clock Source
Bit 6 Bit 5 Receive Clock
0 0 RTxC Pin
0 1 TRxC Pin
1 0 BR Output
1 1 DPLL Output
Table 5–32. Transmit Clock Source
Bit 4 Bit 3 Transmit Clock
0 0 RTxC Pin
0 1 TRxC Pin
1 0 BR Output
1 1 DPLL Output
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