Zilog Z16C35 - Manual (Page 44)

ISCC
User Manual
UM011002-0808
38
or programmed to enter the Search mode. Upon missing this one edge, the DPLL
takes no other action and does not modify its count during the next counting cycle.
7. If the DPLL does not see an edge between the middle of count 12 and the middle of
count 19 in two successive 0 to 31 count cycles, a line error condition is assumed. If
this occurs, the Two Clocks Missing bit in RR10 is set to “1” and latched. At the same
time, the DPLL enters the Search mode. The DPLL makes the decision to enter Search
mode during count 2, where both the receive clock and transmit clock outputs are
LOW. This prevents any glitches on the clock outputs when search mode is entered.
While in search mode, no clock outputs are provided by the DPLL. The Two Clocks
Missing bit in RR10 is latched until a Reset Missing Clock command is issued in
WR14, or until the DPLL is disabled or programmed to enter the Search mode.
While the DPLL is disabled, the transmit clock output of the DPLL may be toggled by
alternately selecting FM and NRZI move in the DPLL. The same is true of the receive
clock.
While the DPLL is in Search mode, the counter remains at count 16, where the receive
output is LOW and the transmit output is LOW. This fact can be used to provide a transmit
clock under software control since the DPLL is in Search mode while it is disabled.
As in NRZI mode, if an adjustment to the counting cycle is necessary, the DPLL modifies
count 5, either deleting it or doubling it. If no adjustment is necessary, the count sequence
proceeds normally.
From the above discussion, together with an examination of FM0 and FM1 data encoding,
it should be obvious that only clock transitions should exist on the receive data pin when
the DPLL is programmed to enter search mode. If this is not the case, the DPLL may
attempt to lock on to the data transitions.
With FM0 encoding this requires continuous “1s” received when leaving Search. In FM1
encoding, it is continuous “0s”; with Manchester encoded data this means alternating “1s”
and “0s.” With all three of these data encoding methods there will always be at least one
transition in every bit cell, and in FM mode the DPLL is designed to expect this transition.
3.5.3 DPLL Operation and Encoding in the Manchester Mode
The ISCC can encode Manchester data using the external logic shown in Figure 3-8, and it
can decode Manchester data using the DPLL. Recall that Manchester encoded data con-
tains a transition at the center of every bit cell; it is the direction of this transition that dis-
tinguishes a “1” from a “0.” Hence, for Manchester data, the DPLL should be in FM
mode, but the receiver should be set up to accept NRZ data. As with the FM modes, when
in the Search Mode the data stream should contain only clock transitions.
Page 38 of 316