Zilog Z16C35 - Manual (Page 76)

ISCC
User Manual
UM011002-0808
70
receiver then removes the “0” following a received succession of five “1s”. Inserted and
removed “0s” are not included in the CRC calculation.
There are two unique bit patterns in SDLC mode besides the flag sequence. They are the
Abort and EOP (End of Poll) sequence. An Abort is a sequence of from seven to thirteen
consecutive “1s” and is used to signal the premature termination of a frame. The EOP is
the bit pattern “11111110”, which is used in loop applications as a signal to a secondary
station that it may begin transmission.
The address field can consist of one or more octets and is used to designate the number of
secondary station to which the commands or data are sent. A control field may follow the
address. The control field is eight bits long and is used to initiate SDLC activities. Data
follows the control field any may consist of any number of bits.
In the SDLC mode, the ISCC operates in the following way. In SDLC mode, frames of
information are opened and closed by a flag. The Flag character has the unique bit pattern
of “01111110”. When transmitting data or CRC, the transmitter automatically performs
zero insertion after five consecutive ones, irrespective of character boundaries. In turn, the
receiver searches the receive data stream for five consecutive “1s” and deletes the next bit
if it is a “0”.
CRC may be used in SDLC mode but only with the CRC-CCITT polynomial. In the
SDLC Mode, the transmitter in the SCC cell automatically inverts the CRC before
trans-mission Because of this inversion, the receiver CRC check results in a non-zero, but
fixed remainder for errorless data. The fixed remainder for this mode is
“0001110100001111” and this is the pattern automatically checked for in the receiver in
this mode. This is consistent with bit-oriented protocols such as SDLC, HDLC, and
ADCCP.
SDLC mode is selected by setting bit D5 of WR4 to “1” and bits D4, D3, and D2 of WR4
to “0”. In addition, the flag sequence must be written to WR7. Additional control bits for
SDLC mode are located in WR10.
4.4.1 SDLC Transmit
In SDLC mode the transmitter moves characters from the transmit buffer to the shift regis-
ter, through the zero inserter, and out the TxD pin. The transmitter does not automatically
send the address byte; it merely encapsulates the data supplied by the processor with flags
and CRC. Also, the processor must load the flag into WR7 as the ISCC does not have a
default flag pattern.
Ordinarily, a frame will be terminated by the ISCC with CRC and a flag but the ISCC may
be programmed to send an abort and a flag in place of the CRC. This option allows the
ISCC to abort a frame transmission in progress if the transmitter is accidentally allowed to
underrun. This is controlled by the Abort/Flag on Underrun bit (D2) in WR10. When this
bit is set to “1” the transmitter will send an abort and a flag in place of the CRC when an
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