Zilog Z16C35 - Manual (Page 22)

ISCC
User Manual
UM011002-0808
16
enabled, the CPU is interrupted when the transmit buffer becomes empty. This implies that
data has shifted from the transmit buffer to the transmitter, thus emptying the transmit buf-
fer. When enabled, the receiver interrupts the CPU in one of three ways:
1. Interrupt on First Receive Character or Special Receive Condition
2. Interrupt on All Receive Characters or Special Receive Condition
3. Interrupt on Special Condition Only
Interrupt on First Character or Special Condition, and Interrupt on Special Condition Only,
are typically used when doing block transfers with the DMA. A Special Receive Condi-
tion is one of the following: receiver overrun, framing error in Asynchronous mode, end-
of-frame in SDLC mode and, optionally, a parity error. The Special Receive Condi-tion
interrupt is different from an Ordinary Receive Character Available interrupt only by the
status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First
Receive Character, an interrupt occurs from Special Receive Conditions any time after the
First Receive Character interrupt.
The main function of the External/Status interrupt is to monitor the signal transitions of
the /CTS, /DCD, and /SYNC pins; however, an External/Status interrupt is also caused by
a Transmit Underrun condition, or a zero count in the baud rate generator, or by the detec-
tion of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode)
sequence in the data stream. The interrupt caused by the Abort or EOP has a special fea-
ture allowing the ISCC to interrupt when the Abort or EOP sequence is detected or termi-
nated. This feature facilitates the proper termination of the current message, correct
initialization of the next message, and the accurate timing of the Abort condition in exter-
nal logic.
2.3.3 DMA Interrupts
Each DMA in the ISCC has two sources of interrupt, which share an IP bit and an IUS bit,
but have independent enables: Terminal Count and Abort. The Abort interrupt is generated
when an active DMA channel is forced to terminate its transfers because /BUSACK is de-
asserted during a transfer. The Terminal Count interrupt is generated when the DMA trans-
fer count reaches zero. The DMA channels themselves are prioritized in a fixed order:
Receive A, Transmit A, Receive B, and Transmit B.
When DMA transfers are used, the on-chip DMA channels transfer data directly to the
transmit buffers or directly from the receive buffers. No other transfers are possible (for
initialization, for example). The request signals from the receivers and transmitters are
hard-wired to the request inputs of the DMA channels internally. Each DMA channel pro-
vides a 32-bit address which is either incremented or decremented with a 16-bit transfer
length. Whenever a DMA channel receives a request from its associated receiver or trans-
mitter and the DMA channel is enabled, the ISCC activates the /BUSREQ signal. Upon
receipt of an active /BUSACK, the DMA channel transfers data between memory and the
SCC cell. This transfer continues until the receiver or transmitter stops requesting a trans-
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