Zilog Z16C35 - Manual (Page 19)

ISCC
User Manual
UM011002-0808
13
2.2.3 Data Transfers
All data transfers to and from the ISCC are done in bytes even though the data may at spe-
cial times occupy the lower or upper byte of the 16-bit bus. Bus transfers as a slave periph-
eral are done differently than bus transfers when the ISCC is the bus master during DMA
transactions. The ISCC is fundamentally an 8-bit peripheral but supports 16-bit buses in
the DMA mode. Slave peripheral and DMA transactions are described in the next para-
graphs.
Data Bus Transfers as a Slave Peripheral: When accessed as a peripheral device (when
the ISCC is not a bus master performing DMA transfers), only 8 bits are transferred. When
the ISCC registers are read, the byte data present on the lower 8 bits of the bus is repli-
cated on the upper 8 bits of the bus. Data is accepted by the ISCC only on the lower 8 bits
of the bus.
ISCC DMA Bus Transfers: During DMA transfers, when the ISCC is bus master, only
byte data is transferred. However, data may be transferred from the ISCC on the upper 8
bits of the bus or on the lower 8 bits of the bus. Moreover, odd or even byte transfers may
be done on the lower or upper 8 bits of the bus. This is programmable and is described
below.
During DMA transfers to memory from the ISCC, byte data only is transferred and the
data appears on the lower 8 bits and is replicated on the upper 8 bits of the bus. Thus the
data may be written to an odd or even byte of the system memory by address decoding and
strobe generation.
During DMA transfers to the ISCC from memory, byte data only is transferred and nor-
mally data is accepted only on the lower 8 bits of the bus. However, the byte swapping
feature may be used to enable data to be accepted on either the lower or upper 8 bits of the
bus. The byte swapping feature is enabled by programming the Byte Swap Enable bit to a
1 in the BCR. The odd/even byte transfer selection is made by programming the Byte
Swap Select bit in the BCR. If Byte Swap Select is a 1, then even address bytes (transfers
where the DMA address has A0 equal 0) are accepted on the lower 8 bits of the bus and
odd address bytes (transfers where the DMA address has A0 equal 1) are accepted on the
upper 8 bits of the bus. If Byte Swap Select is a 0, then even address bytes (transfers where
the DMA address has A0 equal 0) are accepted on the upper 8 bits of the bus and odd
address bytes (transfers where the DMA address has A0 equal 1) are accepted on the lower
8 bits of the bus.
Page 13 of 316