Zilog Z16C35 - Manual (Page 70)

ISCC
User Manual
UM011002-0808
64
receive data FIFO. As previously mentioned, 8-bit sync characters stripped from the data
stream are automatically excluded from CRC calculation.
Some synchronous protocols require that certain characters be excluded from CRC calcu-
lation. This is possible in the ISCC because CRC calculation may be enabled and disabled
on the fly. To give the processor sufficient time to decide whether or not a particular char-
acter should be included in the CRC calculation, the ISCC contains an 8-bit time delay
between the receive shift register and the CRC checker. The logic also guarantees that the
calculation will only start or stop on a character boundary by delaying the enable or dis-
able until the next character is loaded into the receive data FIFO.
To understand how this works refer to Figure 4-9 and the following explanation. Consider
a case where the ISCC receives a sequence of eight bytes, called A, B, C, D, E, F, G and H
with A received first. Now suppose that A is the sync character, that CRC is to be calcu-
lated on B, C, E, and F, and that F is the last byte of this message. A process is used to con-
trol the ISCC as described below.
The Receive Character-Operational Stages:
1. Before A is received the receiver is in Hunt mode and the CRC is disabled. When A is
in the receive shift register it is compared with the contents of WR7. Since A is the
sync character, the bit patterns match and receive leaves Hunt mode, but character A is
not transferred to the receive data FIFO.
2. After 8-bit times, B is loaded into the receive data FIFO. The CRC remains disabled
even though somewhere during the next eight bit times the processor reads B and
enables CRC. At the end of this eight-bit time, B is in the 8-bit delay and C is in the
receive shift register.
3. Character C is loaded into the receive data FIFO and at the same time the CRC
checker becomes enabled. During the next eight-bit-time, the processor reads C and
since CRC is enabled within this period, the ISCC has calculated CRC on character B;
character C is in the 8-bit delay and D is in the Receive Shift register. D is then loaded
into the receive data FIFO and at some point during the next eight-bit-time the proces-
sor reads D and disables CRC. At the end of these eight-bit-times CRC has been cal-
culated on C, character D is in the 8-bit delay and E is in the Receive Shift register.
4. Now E is loaded into the receive data FIFO. During the next eight-bit-times the pro-
cessor reads E and enables the CRC. During this time E shifts into the 8-bit delay, F
enters the Receive Shift register and CRC is not being calculated on D. After these
eight-bit-times have elapsed, E is in the 8-bit delay, and F is in the Receive Shift regis-
ter. Now F is transferred to the receive data FIFO and CRC is enabled. During the next
eight-bit-times the processor reads F and leaves the CRC enabled. The processor is
usually aware that this is the last character in the message and so prepares to check the
result of the CRC computation. However, another sixteen bit-times are required before
CRC has been calculated on all of character F.
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