Zilog Z16C35 - Manual (Page 14)

ISCC
User Manual
UM011002-0808
8
Phase-Locked Loop, the crystal oscillator, the baud rate generator, or the transmit clock in
the output mode.
/CE. Chip Enable (input, active Low). This signal selects the ISCC for a peripheral read or
write operation. This signal is ignored when the ISCC is bus master.
AD15-AD0. Data bus (bidirectional, tri-state). These lines carry data and commands to
and from the ISCC.
/RD. Read (bidirectional, active Low). When the ISCC is a peripheral (i.e., bus slave), this
signal indicates a read operation and when the ISCC is selected, enables the ISCC’s bus
drivers. As an input, /RD indicates that the CPU wants to read from the ISCC read regis-
ters. During the Interrupt Acknowledge cycle, /RD gates the interrupt vector onto the bus
if the ISCC is the highest priority device requesting an interrupt. When the ISCC is the bus
master, this signal is used to read data. As an output, after the ISCC has taken control of
the system buses, /RD indicates a DMA-controlled read from a memory or I/O port
address.
/WR. Write (bidirectional, active Low). When the ISCC is selected, this signal indicates a
write operation. As an input, this indicates that the CPU wants to write control or com-
mand bytes to the ISCC write registers. As an output, after the ISCC has taken control of
the system buses /WR indicates a DMA-controlled write to a memory or I/O port address.
/DS. Data Strobe (bidirectional, active Low). A Low on this signal indicates that the
AD15-AD0 bus is used for data transfer. When the ISCC is not in control of the system
bus and the external system is transferring information to or from the ISCC, /DS is a tim-
ing input used by the ISCC to move data to or from the AD15-AD0 bus. Data is written
into the ISCC by the external system on the High to Low /DS transition. Data is read from
the ISCC by the external system while /DS is Low. There are no timing requirements
between /DS as an input and ISCC clock; this allows use of the ISCC with a system bus
which does not have a bussed clock.
During a DMA operation when the ISCC is in control of the system, /DS is an output gen-
erated by the ISCC and used by the system to move data to or from the AD15-AD0 bus.
When the ISCC has bus control, it writes to the external system by placing data on the
AD15-AD0 bus before the High-to-Low /DS transition and holds the data stable until after
the Low-to-High /DS transition; while reading from the external system, the Low-to-High
transition of /DS inputs data from the AD15-AD0 bus into the ISCC.
R//W. Read/Write (bidirectional). Read polarity is High and write polarity is Low. When
the ISCC is not in control of the system bus and the external system is transferring infor-
mation to or from the ISCC, R//W is a status input used by the ISCC to determine if data is
entering or leaving on the AD15-AD0 bus during /DS time. In such a case, Read (High)
indicates that the system is requesting data from the ISCC and Write (Low) indicates that
the system is presenting data to the ISCC. The only timing requirements for R//W as an
input are defined relative to /DS. When the ISCC is in control of the system bus, R//W is
an output generated by the ISCC, with Read (high) indicating that data is being requested
Page 8 of 316