Zilog Z16C35 - Manual (Page 194)

Application Note
The Z180™ Interfaced with the SCC at MHZ
7-17
7
During an Interrupt Acknowledge cycle, the SCC requires
both /INTACK and /RD to be active at certain times. Since
the Z180 does not issue either /INTACK or /RD, external
logic generates these signals.
The Z180 is in a Wait condition until the vector is valid. If
there are other peripherals added to the interrupt priority
daisy chain, more Wait states may be necessary to give it
time to settle. Allow enough time between /INTACK active
and /RD active for the entire daisy chain to settle.
There is no need of decoding the RETI instruction used by
the Z80 peripherals since the SCC daisy chain does not
use IP, except during Interrupt Acknowledge. The SCC
and other Z8500 peripherals have commands that reset
the individual IUS flag.
External Interface for Interrupt Acknowledge Cycle: The
bottom half of Figure 14 is the interface logic for the
Interrupt Acknowledge cycle.
Table 10. 10 MHz SCC Timing Parameters for Interrupt Acknowledge Cycle
No Symbol Parameter Min Max Units
13 TsIAi(RD) /INTACK Low to /RD Low Setup 130 ns
14 ThIA(RD) /INTACK High to /RD High Hold 0 ns
15 ThIA(PC) /INTACK to PCLK High Hold 30 ns
38 TwRDA /INTACK Low to /RD Low Delay 125 ns
(Acknowledge)
39 TwRDA /RD (Acknowledge) Width 125 ns
40 TdRDA(DR) /RD Low (Acknowledge) to
Read Data Valid Delay 120 ns
41 TsIEI(RDA) IEI to /RD Low (Acknowledge) 95 ns
Setup Time
42 ThIEI(RDA) IEI to /RD High (Acknowledge) 0 ns
Hold Time
43 TdIEI(IEO) IEI to IEO Delay 175 ns
Table 11. Z180 Timing Parameters Interrupt Acknowledge Cycles (Worst Case Z180)
No Symbol Parameter Min Max Units
10 tM1D1 Clock High to /M1 Low 60 ns
14 tM1D2 Clock High to /M1 High 60 ns
15 tDRS Data to Clock Setup 25 ns
16 tDRH Data Read Hold Time 0 ns
28 tIOD1 Clock LOW to /IORQ Low 50 ns
29 tIOD2 Clock LOW to /IORQ High 50 ns
30 tIOD3 /M1 Low to /IORQ Low Delay 200 ns
Note: Parameter numbers in this table are the numbers in the Z180 technical manual.
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UM011002-0808