Zilog Z16C35 - Manual (Page 110)

ISCC
User Manual
UM011002-0808
104
For five or less bits per character selection in WR5, the following encoding is used in the
data sent to the transmitter. D is the data bit(s) to be sent.
Bit 4 is the Send Break control bit
When set, this bit forces the TxD output to send continuous “0s” beginning with the fol-
lowing transmit clock, regardless of any data being transmitted at the time. This bit func-
tions whether or not the transmitter is enabled. When reset, TxD continues to send the
contents of the Transmit Shift register, which might be syncs, data, or all “1s.” If this bit is
set while in the X21 mode (Monosync and Loop mode selected) and character synchroni-
zation is achieved in the receiver, this bit is automatically reset and the transmitter begins
sending syncs or data. This bit can also be reset by a channel or hardware reset.
Bit 3 is Transmit Enable
Data is not transmitted until this bit is set, and the TxD output sends continuous “1s”
unless Auto Echo mode or SDLC Loop mode is selected. If this bit is reset after transmis-
sion started, the transmission of data or sync characters is completed. If the transmitter is
disabled during the transmission of a CRC character, sync or flag characters are sent
instead of CRC. This bit is reset by a channel or hardware reset.
This bit determines whether or not CRC is calculated on a transmit character. If this bit is
set at the time the character is loaded from the transmit buffer to the Transmit Shift regis-
ter, CRC is calculated on that character. CRC is not automatically sent unless this bit is set
when the transmit underrun exists.
5.4.7 Write Register 6 (Sync Characters or SDLC Address Field)
WR6 is programmed to contain the transmit sync character in the Monosync mode, the
first byte of a 16-bit sync character in the External Sync mode. WR6 is not used in asyn-
chronous modes. In the SDLC modes, it is programmed to contain the secondary address
field used to compare against the address field of the SDLC Frame. In SDLC mode, the
ISCC does not automatically transmit the stations address at the beginning of a response
frame. Bit positions for WR6 are shown in Figure 5-8.
D7 D6 D5 D4 D3 D2 D1 D0 Description
1 1 1 1 0 0 0 D Sends one data bit
1 1 1 0 0 0 D D Sends two data bits
1 1 0 0 0 D D D Sends three data bits
1 0 0 0 D D D D Sends four data bits
0 0 0 D D D D D Sends five data bits
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