Zilog Z16C35 - Manual (Page 147)

ISCC
User Manual
UM011002-0808
141
Figure 5–64. Transmit DMA Count Registers
5.6.11 Receive DMA Address Registers A, B
There are two sets of Receive DMA Address Registers, one set for Receive DMA Channel
A and one set for Receive DMA Channel B. Each set consists of four registers, one for
address bits 7-0, one for address bits 15-8, one for address bits 23-16, and one for address
bits 31-24 as shown in Figure 5-36. These registers are read/write.
(A) LSB
Address: 01010 (Low Byte)
D6 D7 D5 D4 D3 D2 D1 D0
Tx A Cnt0
Tx A Cnt1
Tx A Cnt2
Tx A Cnt3
Tx A Cnt4
Tx A Cnt5
Tx A Cnt6
Tx A Cnt7
(B) MSB
Address: 01011 (High Byte)
D6 D7 D5 D4 D3 D2 D1 D0
Tx A Cnt8
Tx A Cnt9
Tx A Cnt10
Tx A Cnt11
Tx A Cnt12
Tx A Cnt13
Tx A Cnt14
Tx A Cnt15
(A) LSB
Address: 01110 (Low Byte)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B Cnt0
Tx B Cnt1
Tx B Cnt2
Tx B Cnt3
Tx B Cnt4
Tx B Cnt5
Tx B Cnt6
Tx B Cnt7
(B) MSB
Address: 01111 (High Byte)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B Cnt8
Tx B Cnt9
Tx B Cnt10
Tx B Cnt11
Tx B Cnt12
Tx B Cnt13
Tx B Cnt14
Tx B Cnt15
Transmit DMA Count Register Channel A
Transmit DMA Count Register Channel B
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