Zilog Z16C35 - Manual (Page 31)

ISCC
User Manual
UM011002-0808
25
Note: *Address in this Table is AD5-AD1 in the Multiplexed Bus with the Shift Left mode selected, AD4-AD0 in the
Multiplexed Bus with the Shift Right mode selected, and D4 -D0 of the Channel Command/Address Register in
the Non-multiplexed Bus mode.
2.4.6 DMA Register Access, Non-Multiplexed Bus Mode
The registers in the DMA cell in the non-multiplexed bus mode are accessed in a two-step
process, using a Register Pointer to perform the addressing. To access a particular register,
the pointer bits must be set by writing to the Channel Command /Address Register bits 4
through 0. After the pointer bits are set, the next read or write cycle to the DMA cell will
access the desired register. At the conclusion of this read or write cycle, the pointer bits are
reset to “0s,” so that the next access will be to the Channel Command/Address Register.
The fact that the pointer bits are reset to “0,” unless explicitly set otherwise, means that the
Channel Command/Address Register may be accessed in a single cycle. That is, it is not
necessary to write the pointer bits with “0” before accessing the Channel Command/
Address Register. This permits single access DMA enabling and resetting the highest IUS
through the encoded DMA Commands.
2.4.7 Notes on Pointer Accesses
The non-multiplexed bus accesses are accomplished as described in the preceding para-
graphs using the DMA pointer for the DMA cell and the SCC cell pointer for channels A
and B. These two pointers are completely independent. If one of these pointers is written
to with a pointer value in preparation for a read or write to the selected register, the pointer
will hold its value until the corresponding cell is accessed. For example, suppose the SCC
cell pointer is written to in preparation to read an SCC cell register in the next (or even
subsequent) software program steps. Before this SCC cell read takes place, a DMA inter-
rupt occurs and the program enters the interrupt service routine prior to the SCC register
read. In the interrupt service routine, several DMA register accesses are made. When the
program exits the interrupt service routine and returns to the interrupted process, the regis-
ter access to the SCC cell register proceeds correctly; the pointer was left unaltered. A
converse situation is true for the DMA cell.
It should be clear, however, that if an interrupt routine is invoked between the pointer
write and the register access, there can be conflict if the same cell is accessed in the inter-
rupt service routine. Assume in the above example that the interrupt service routine
accesses the SCC cell also. Since the pointer has already been written, a second write (the
one in the interrupt service routine) will not write to the pointer in WR0 but will write to
the pointed to register. Subsequent register access will also be incorrect. This suggests that
the pointer write and subsequent register access be an uninterruptable pair and that the
SCC Cell and DMA cell or the processor interrupts be disabled during the register access
sequence.
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