Zilog Z16C35 - Manual (Page 58)

ISCC
User Manual
UM011002-0808
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mand is issued, until the first transmit clock edge after this bit is reset. The transmit clock
edges referred to here are those that define transmitted bit cell boundaries.
An additional status bit for use in Asynchronous mode is available in bit D0 or RR1. This
bit, called All Sent, is set when the transmitter is completely empty and any previous data
or stop bits have reached the TxD pin. The All Sent bit can be used by the processor as an
indication that the transmitter may be safely disabled.
The initialization sequence for the transmitter in asynchro-nous mode is given in
Table 4-3.
At this point other registers should be initialized according to the hardware design such as
clocking, I/O mode, etc. When all this is completed, the transmitter may be enabled by set-
ting WR5(3) = 1. Also note that the transmitter and receiver may be initialized at the same
time.
The number of bits/char is selected by WR3, bits 6-7.
4.2.2 Asynchronous Reception
During reception, the start and stop bits are stripped away and checked for errors, leaving
only the working data for CPU interaction.
The receiver always checks for one stop bit. If after character assembly the receiver finds
this stop bit to be a “0”, the Framing Error bit in the receive error FIFO is set at the same
time that the character is transferred to the receive data FIFO. This error bit accompanies
the data to the top of the FIFO, where it generates a special receive condition. The Fram-
ing Error bit is not latched, and so must be read in RR1 before the accompanying data is
read.
Table 4–11. Initialization Sequence for the Transmitter in Asynchronous Mode
Reg Bit No Description
WR4 3, 2 Select Async Mode and the number of stop bits*
0, 1 Select parity*
6, 7 Select clock mode*
WR3 5 Select Auto Enable Mode*
WR5 1 Select modem control (RTS)
4 Select break generation
6, 5 Select number of bits/char for transmitter
Note: * Initializes transmitter and receiver simultaneously
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