Zilog Z16C35 - Manual (Page 29)

ISCC
User Manual
UM011002-0808
23
There are two address decoding modes: shift left and shift right. In shift left mode, the
register address is decoded from AD5-AD1. This mode is set by a hardware reset. In Shift
right mode, the register address is decoded from AD4-AD0. The shift right/shift left selec-
tion for the DMA is located in the Bus Configuratin Register, bit D0. When set, this bit
programs the Shift Right mode for the DMA and when reset, this bit programs the Shift
Left Mode.
The address map for the DMA registers is shown in Table 2-6. This Table is also applica-
ble to the non-multiplexed bus mode.
Page 23 of 316