Zilog Z16C35 - Manual (Page 246)

Application Note
Serial Communication Controller (SCC
™
): SDLC Mode of Operation
11-3
1
Notes on Figure 1:
1. The SCC has two possible idle states, Mark idle
(contiguous logic 1) or Flag idle (repeating flag pattern
7EH). In this figure, the SCC has to be switched to flag
idle in order to send the opening flag of the frame.
Care must be taken not to put the first data byte (in this
case, address 81H) into the Transmit Buffer too soon
after the switchover from Mark idle to Flag idle has
been made; otherwise, the data may be loaded into
the Transmit Shift Register before the flag is loaded.
To ensure that this cannot happen, a delay must be
executed before the first data byte is put into the
buffer. The delay time is dependent on the data rate
and a safe minimum duration is 8 bit-times.
2. Transmit Buffer Empty Interrupt for 81H. At this point
the data has just been transferred to the Transmit Shift
Register and data 42H is written to the Transmit
Buffer.
3. The time between the first data byte being transferred
to the Shift Register and the first bit appearing at the
TxD pin is always six bit-times.
4. Transmit Buffer Empty Interrupt for data 42H. Data
0FFH is written to the Transmit Buffer at this point.
5. Transmit Buffer Empty Interrupt for data 0FFH. Data
42H is written to the Transmit Buffer at this point.
6. The time between interrupts depends on the data
character length and the number of zero insertions in
the character. For 8 bits/character it can vary between
8 and 10 bit-times. The particular instance shown
corresponds to the single zero insertion when the byte
0FFH is transmitted.
7. Transmit Buffer Empty Interrupt for data 42H. Since
this is the last byte to be transmitted, the Reset
Transmit Interrupt Pending command is issued
instead of writing another byte to the Transmit Buffer.
8. Transmitter Underrun/EOM Interrupt. This occurs
when both the Transmit Shift Register and the
Transmit Buffer are empty. It is an External/Status
interrupt. The data sent when this occurs is
summarized in the table below:
9. The transmitted CRC is 16 bits long provided that
there are no zero insertions. In theory it could be as
long as 19 bits.
10. The last interrupt generated occurs after the CRC is
shifted out of the transmitter and a flag is loaded to be
sent. It is a Transmit Buffer Empty Interrupt. If another
frame is to be transmitted, the first character of the
next frame can be loaded. The two frames will then be
separated by a single flag (Back-to-back frame).
11. If the SCC is set up for mark on idle and a new
character is not loaded when the last interrupt occurs,
only a single flag is sent.
Abort/Flag on Tx Underrun/EOM Latch Data
Underrun bit State when Underrun occurs Sent
0 Reset CRC and Flag
1 Reset Abort and Flag
0 Set Flags
1 Set Flags
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