Zilog Z16C35 - Manual (Page 54)

ISCC
User Manual
UM011002-0808
48
The incoming data then passes through the Sync register and is compared to a sync charac-
ter stored in WR6 or WR7 (depending on which mode it is in). The Monosync mode
matches the sync character programmed in WR7 and the character assembled in the
Receive Sync register to establish synchronization.
Synchronization is achieved differently in the Bisync mode. Incoming data is shifted to the
Receive Shift register while the next eight bits of the message are assembled in the
Receive Sync register. If these two characters match the programmed characters in WR6
and WR7, synchronization is established. Incoming data can then bypass the Receive Sync
register and enter the 3-bit delay directly.
The SDLC mode of operation uses the receive Sync register to monitor the receive data
stream and to perform zero deletion when necessary; i.e., when five continuous “1s” are
received, the sixth bit is inspected and deleted from the data stream if it is “0”. The seventh
bit is inspected only if the sixth bit equals one. If the seventh bit is “0”, a flag sequence has
been received and the receiver is synchronized to that flag. If the seventh bit is a “1” an
abort or an EOP (End Of Poll) is recognized, depending upon the selection of either the
normal SDLC mode or SDLC Loop mode.
The same path is taken by incoming data for both SDLC modes. The reformatted data
enters the 3-bit delay and is transferred to the Receive Shift register. The SDLC receive
operation begins in the hunt phase by attempting to match the assembled character in the
Receive Shift Register with the flag pattern in WR7. Then the flag character is recognized,
subsequent data is routed through the same path, regardless of character length.
Either the CRC-16 or CRC-SDLC cyclic redundancy check (CRC) polynomial can be
used for both Monosync and Bi-sync modes, but only the CRC-SDLC polynomial is used
for SDLC operation. The data path taken for each mode is also different. Bisync protocol
is a byte-oriented operation that requires the CPU to decide whether or not a data character
is to be included in CRC calculation. An 8-bit delay in all synchronous modes except
SDLC is allowed for this process. In SDLC mode, all bytes are included in the CRC calcu-
lation.
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