Zilog Z16C35 - Manual (Page 164)

Application Note
Interfacing Z80 ® CPUs to the Z8500 Peripheral Family
6
Z90H CPU TO Z8500 PERIPHERALS
During an I/O Read cycle, there are three Z8500
parameters that must be satisfied. Depending upon the
loading characteristics of the /RD signal, the designer may
need to delay the leading (falling) edge of /RD to satisfy the
Z8500 timing parameter TsA(RD) (Addresses Valid to /RD
Setup). Since Z80H timing parameters indicate that the
/RD signal may go Low after the falling edge of T2, it is
recommended that the rising edge of the system clock be
used to delay /RD (if necessary). The CPU must also be
placed into a Wait condition long enough to satisfy
TdA(DR) (Address Valid to Read Data Valid Delay) and
TdRDf(DR) (/RD Low to Read Data Valid Delay).
During an I/O Write cycle, there are three other Z8500
parameters that must be satisfied. Depending upon the
loading characteristics of the /WR signal and the data bus,
the designer may need to delay the leading (falling) edge
of /WR to satisfy the Z8500 timing parameters TsA(WR)
(Address Valid to /WR setup). Since Z80H timing
parameters indicate that the /WR signal may go Low after
the falling edge of T2, it is recommended that the rising
edge of the system clock be used to delay /WR (if
necessary). This delay will ensure that both parameters
are satisfied. The CPU must also be placed into a Wait
condition long enough to satisfy TwWR1 (/WR Low Pulse
Width). Assuming that the /WR signal is delayed, only two
additional Wait states are needed during an I/O Write cycle
when interfacing the Z80H CPU to the Z8500 peripherals.
To simplify the I/O interface, the designer can use the
same number of Wait states for both I/O Read and I/O
Write cycles. Figure 6 shows the minimum Z80H CPU to
Z8500 peripheral interface timing for the I/O cycles
(assuming that the same number of Wait states are used
for both cycles and that both /RD and /WR need to be
delayed). Figure 8 shows two suits that can be used to
delay the leading (falling) edge of either the /RD or the /WR
signals. There are several ways to place the Z80A CPU
into a Wait condition (such as counters or shift registers to
count system clock pulses), depending upon whether or
not the use wants to place Wait states in all I/O cycles, or
only during Z8500 I/O cycles. Tables 3 and 10 list the
Z8500 peripheral and the Z80H CPU timing parameters
(respectively) of concern during the I/O cycles. Tables 13
and 14 list the equations used in determining if these
parameters are satisfied. In generating these equations
and the values obtained from them, the required number
of Wait states was taken into account. The reference
numbers in Tables 3 and 10 refer to the timing diagram of
Figure 6.
Table 10. Z80H Timing Parameter I/O Cycles
Equation Min Max Units
TcC Clock Cycle Period 125
TwCh Clock Cycle High Width 55 ns
TfC Clock Cycle Fall Time 10 ns
TdCr(A) Clock High to Address Valid 80 ns
TdCr(RDf) Clock High to /RD Low 60 ns
TdCr(IORQf) Clock High to /IORQ Low 55 ns
TdCr(WRf) Clock High to /WR Low 55 ns
5. TsD(Cf) Data to Clock Low Setup 30 ns
Table 11. Parameter Equations
Z8500
Parameter Z80H
Equation
Value Units
TsA(RD) 2TcC-TdCr(A) 170 min ns
TdA(DR) 6TcC+TwCh-TdCr(A)-TsD(Cf) 695 min ns
TdRDf(DR) 4TcC+TwCh-TsD(Cf) 523 min ns
TwRD1 4TcC+TwCh+TfC-TdCr(RDf) 503 min ns
TsA(WR) /WR - delayed
2TcC-TdCr(A)
170 min ns
TsDW(WR) >0 min ns
TwWR1 4TcC+TwCh+TfC 563 min ns
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