Zilog Z16C35 - Manual (Page 115)

ISCC
User Manual
UM011002-0808
109
Bit 7 is the CRC Presets 1//0 select bit
This bit specifies the initialized condition of the receive CRC checker and the transmit
CRC generator. If this bit is set to “1,” the CRC generator and checker are preset to “1.” If
this bit is set to “0,” the CRC generator and checker are preset to “0.” Either option can be
selected with either CRC polynomial. In SDLC mode, the transmitted CRC is inverted
before transmission and the received CRC is checked against the bit pattern
“0001110100001111.” This bit is reset by a channel or hardware reset. This bit is ignored
in Asynchronous mode.
Bits 6 and 5 are the Data Encoding select bits
These bits control the coding method used for both the transmitter and the receiver, as
illustrated in Table 5-8. All of the clocking options are available for all coding methods.
The DPLL in the ISCC is useful for recovering clocking information in NRZI and FM
modes. Any coding method can be used in X1 clock mode. A hardware reset forces NRZ
mode. Timing for the various modes is shown in Figure 5-12.
Figure 5–41. NRZ (NRZ1), FM1 (FM0) Timing
Table 5–30. Data Encoding
Bit 6 Bit 5 Encoding
0 0 NRZ
0 1 NRZI
1 0 FM1 (transition = 1)
1 1 FM0 (transition = 0)
Manchester
FM0
FM1
NRZ1
NRZ
Data 1 0 1 0 1 0
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