Zilog Z16C35 - Manual (Page 127)

ISCC
User Manual
UM011002-0808
121
(seven or more “1s”), then reset automatically at the termination of the Abort sequence. In
either case, if the Break/Abort IE bit is set, an External/Status interrupt is initiated. Unlike
the remainder of the External/Status bits, both transitions are guaranteed to cause an Exter-
nal/Status interrupt, even if another External/Status interrupt is pending at the time these
transitions occur. This procedure is necessary because Abort or Break conditions may not
persist.
Bit 6 is the Transmit Underrun/EOM status
This bit is set by a channel or hardware reset and when the transmitter is disabled or a
Send Abort command is issued. This bit can only be reset by the reset Tx Underrun/EOM
Latch command in WR0. When the Transmit Underrun occurs, this bit is set and causes an
External/Status interrupt (if the Tx Underrun/EOM IE bit is set).
Only the 0-to-1 transition of this bit causes an interrupt. This bit is always “1” in Asyn-
chronous mode, unless a reset Tx Underrun/EOM Latch command has been erroneously
issued. In this case, the Send Abort command can be used to set the bit to one and at the
same time cause an External/Status interrupt.
Bit 5 is the Clear to Send pin status
If the CTS IE bit in WR15 is set, this bit indicates the state of the /CTS pin while no inter-
rupt is pending latches the state of the /CTS pin and generates an External/Status interrupt.
Any odd number of transitions on the /CTS pin, while another External/Status interrupt is
pending, also causes an External/Status interrupt condition. If the CTS IE bit is reset, it
merely reports the current unlatched state of the /CTS pin.
Bit 4 is the SYNC/Hunt status
The operation of this bit is similar to that of the CTS bit, except that the condition moni-
tored by the bit varies depending on the mode in which the ISCC is operating.
When the XTAL oscillator option is selected in asynchronous modes, this bit is forced to
“0” (no External/Status interrupt is generated). Selecting the XTAL oscillator in synchro-
nous or SDLC modes had no effect on the operation of this bit.
The XTAL oscillator should not be selected in External Sync mode.
In Asynchronous mode, the operation of this bit is identical to that of the CTS status bit,
except that this bit reports the state of the /SYNC pin.
In External sync mode the /SYNC pin is used by external logic to signal character syn-
chronization. When the Enter Hunt Mode command is issued in External Sync mode, the /
SYNC pin must be held High by the external sync logic until character synchronization is
achieved. A High on the /SYNC pin holds the Sync/Hunt bit in the reset condition.
When external synchronization is achieved, /SYNC must be driven Low on the second ris-
ing edge of the Receive Clock after the last rising edge of the Receive Clock on which the
last bit of the receive character was received. Once /SYNC is forced Low, it is good prac-
tice to keep it Low until the CPU informs the external sync logic that synchronization has
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