Zilog Z16C35 - Manual (Page 88)

ISCC
User Manual
UM011002-0808
82
If SDLC loop is deselected, the ISCC is designed to exit from the loop gracefully. When
SDLC Loop mode is deselected by writing to WR10; the ISCC waits until the next polling
cycle to remove the one-bit time delay.
If a polling cycle is in progress at the time the command is written, the ISCC finishes
sending any message that it may be transmitting, ends with an EOP, and disconnects TxD
from RxD. If no message was in progress, the ISCC immediately disconnects TxD from
RxD.
Once the ISCC™ is not sending on the loop, an exit from the loop is accomplished by set-
ting the Loop Mode bit in WR10 to “0”, and at the same time writing the Abort/Flag on
Underrun and Mark/Flag idle bits with the desired values. The ISCC will revert to normal
SDLC operation as soon as an EOP is received, or immediately, if the receiver is already
in Hunt mode because of the receipt of an EOP.
To ensure proper loop operation after the ISCC goes off the loop, and until the external
relays take the ISCC completely out of the loop, the ISCC should be programmed for
Mark idle instead of Flag idle. When the ISCC goes off the loop, the On-Loop bit is reset.
Note: With NRZI encoding, removing the stations from the loop (removing the one-bit
time delay) may cause problems further down the loop because of extraneous transitions
on the line. The ISCC avoids this problem by making transparent adjustments at the end of
each frame it sends in response to an EOP. A response frame from the ISCC is terminated
by a flag and EOP. Normally, the flag and the EOP share a zero, but if such sharing would
cause the RxD and TxD pins to be of opposite polarity after the EOP, the ISCC adds
another zero between the flag and the EOP. This causes an extra line transition so that RxD
and TxD are identical after the EOP is sent. This extra zero is completely transparent
because it only means that the flag and the EOP no longer share a zero. All that a proper
loop exit needs, therefore, is the removal of the one-bit delay.
The ISCC allows the user the option of using NRZI in SDLC Loop mode by programming
WR10 appropriately. With NRZI encoding, the outputs of secondary stations in the loop
may be inverted from their inputs because of messages that they have transmitted.
The initialization sequence for the SCC cell in SDLC Loop mode is similar to the
sequence used in SDLC mode, except that it is somewhat longer. The processor should
program WR4 first, to select SDLC mode, and then WR10 to select the CRC preset value
and program the Mark/Flag idle bit. The Loop Mode and Go Active On Poll bits in WR10
should not be set to “1” yet. The flag is written in WR7 and the various options are
selected in WR3 and WR5. At this point the other registers should be initialized as neces-
sary, as shown in Table 4-14.
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