Zilog Z16C35 - Manual (Page 90)

ISCC
User Manual
UM011002-0808
84
point the processor may either write the first character to the transmit buffer and wait for a
transmit buffer empty condition, or wait for the Break/Abort and Hunt bits to be set in
RR10 and the Loop Sending bit to be set in RR10 before writing the first data to the trans-
mitter. The Go Active On Poll bit should be set to “0” after the transmission of the frame
has begun. To go off of the loop, the processor should set the Go Active On Poll bit in
WR10 to “0” and then wait for the Loop Sending bit in RR10 to be set to “0”. At this point
the Loop Mode bit (D1) in WR10 is set to “0” to request an orderly exit from the loop. The
ISCC will exit SDLC Loop mode when seven consecutive “1s” have been received; at the
same time the Break/Abort and Hunt bits in RR0 will be set to “1”, and the On Loop bit in
RR10 will be set to “0”.
4.4.4 SDLC Loop Mode Receive
SDLC Loop mode is quite similar to SDLC mode except that two additional control bits
are used. They are the Loop Mode bit (D1) and the Go Active on Poll bit (D4) in WR10.
In addition to these two extra control bits, there are also two status bits in RR10. They are
the On Loop bit (D1) and the Loop Sending bit (D4).
Before Loop mode is selected both the receiver and transmitter must be completely initial-
ized for SDLC operation. Once this is done, Loop mode is selected by setting bit D1 of
WR10 to “1”. At this point the ISCC connects TxD to RxD with only gate delays in the
path. At the same time a flag is loaded into the Transmit Shift register, and is shifted to the
end of the zero inserter, ready for transmission. The ISCC will remain in this state until the
Go Active on Poll bit (D4) in WR10 is set to “1”. When this bit is set to “1” the receiver
begins looking for a sequence of seven consecutive “1s”, indicating either an EOP or an
idle line. When the receiver detects this condition the Break/Abort bit in RR0 is set to “1”
and a one-bit time delay is inserted in the path from RxD to TxD. The On Loop bit in
RR10 is also set to “1” at this time, and the receiver enters the Hunt mode. The ISCC can-
not transmit on the loop until a flag is received, causing the receiver to leave Hunt mode,
and another EOP (bit pattern “11111110”) is received. The ISCC is now on the loop and
capable of transmitting on the loop. As soon as this status is recognized by the processor,
the Go Active On Poll bit in WR10 should be set to “0” to prevent the ISCC from trans-
mitting on the loop without the consent of the processor.
4.4.5 SDLC Loop Mode Transmit
To transmit a message on the loop, the Go Active On Poll bit in WR10 must be set to “1”.
Once this is done, the ISCC will change the next received EOP into a Flag and begin trans-
mitting on the loop.
When the EOP is received, the Break/Abort and Hunt bits in RR0 will be set to “1”, and
the Loop Sending bit in RR10 will also be set to “1”. Data to be transmitted may be writ-
ten after the Go Active On Poll bit has been set or after the receiver enters Hunt mode.
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