Zilog Z16C35 - Manual (Page 221)

Application Note
The Zilog Datacom Family with the 80186 CPU
9-11
8
The pin-out of the J5-J10 connectors is fairly consistent,
but of necessity not identical because of differences among the various serial controllers:
The ground pins are included as signal references with off-
board hardware.
When interconnecting between two connectors among J5-
J10, DO NOT jumper corresponding pins straight across,
as this connects outputs to outputs and inputs to inputs.
Rather, connect at least each pin 1 to the other pin 2, and
enough opposing inputs and outputs as needed to make
the communication protocol meaningful.
The pin-out of the 12-pin J13-J15 connectors is similar to
that of J5-J10, but more extensive. To allow for the “DCE”
connectors that were added in revision “B” of the board,
J13 and J14 are 16-pin headers and J15 is a 14-pin one:
Table 8. On-Board Line Driver/Receiver Connectors
To use a serial chip controller with the
following on-chip serial interface: Connect the connector(s)
from the previous table to:
J1A or J1B EIA-RS-232 Console J13
J2A or J2B EIA-RS-232 J14
RS-422 differential: J3A or J3B EIA-530 or J4 Circular-8 (DIN) J15
Table 9. Pin Assignments of Standard Controller Connectors
J5: (E)SCC J6: (E)SCC J7,8: ISCC J9: IUSC J10: MUSC J12: USC
Pin# A pin B pin pin pin or USC A pin B pin
1 TxD TxD TxD TxD TxD TxD
2 RxD RxD RxD RxD RxD RxD
3 /RTS /RTS /RTS (N/C) /RxACK /RxACK
4 /CTS /CTS /CTS /CTS /CTS /CTS
5 /DTR /DTR or (N/C) [1] /DTR (N/C) /TxACK /TxACK
6 /DCD /DCD /DCD /DCD /DCD /DCD
7 /SYNC /SYNC /SYNC (SYSCLK) (SYSCLK) (SYSCLK)
8 /RTxC /RTxC /RTxC /RxC /RxC /RxC
9 /TRxC /TRxC /TRxC /TxC /TxC /TxC
10 GND GND GND GND GND GND
11 NA NA NA /TxREQ /TxREQ /TxREQ
12 NA NA NA /RxREQ /RxREQ /RxREQ
Note:
[1] Controlled by the J24 jumper block: must be N/C if (E)SCC channel B transmitter is to be handled by an 80186 DMA channel.
Table 10. Pin Assignments of Line Driver/Receiver Connectors
J13-J14 J13-J14 J15 J15
Pin # DTE signal DCE signal DTE signal DCE signal Direction/where used
1 TxD RxD TxD RxD Output to J1-J4
2 RxD TxD RxD TxD Input from J1-J4
3 /RTS /CTS /RTS /CTS Output to J1-J3
4 /CTS /RTS /CTS /RTS Input from J1-J4 [3]
5 /DTR /DSR /DTR /DSR Output to J1-J4
6 /DSR /DTR /DSR /DTR Input from J1-J4
Note:
[3] Various conventions have been used to combine synchronous clock inputs and modem control inputs on Apple Macintosh connectors
similar to J4, as described in a later section.
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