Zilog Z16C35 - Manual (Page 225)

Application Note
The Zilog Datacom Family with the 80186 CPU
9-15
8
JUMPER SUMMARY
Table 12 includes only those connector blocks intended to
be populated by 2-pin option jumpers. J1-J15 and J26 are actual connectors meant for use with cables, jumper wires,
or wire-wrapped connections.
Table 12. Two-Pin Option Jumpers
Jumpers Installed Open
J9-J7 thru -9 7 to 8: 80186 SYSCLK is IUSC /RxC 8: Something else on /RxC, or N/C
7 to 9: 80186 SYSCLK is IUSC /TxC 9: Something else on /TxC, or N/C
J10-J7 thru -9 7 to 8: 80186 SYSCLK is MUSC (USC A) /RxC 8: Something else on /RxC, or N/C
7 to 9: 80186 SYSCLK is MUSC (USC A) /TxC 9: Something else on /TxC, or N/C
J12-J7 thru -9 7 to 8: 80186 SYSCLK is USC B /RxC 8: Something else on /RxC, or N/C
7 to 9: 80186 SYSCLK is USC B /TxC 9: Something else on /TxC, or N/C
J16-J1 thru -3 1 to 2: J3, J4 TxD driven when RTS Must install one or the other
2 to 3: J3, J4 TxD, RTS driven full-time
J17-J1 to -2 Unbalanced DCD- on J3 or J4 Differential DCD+, DCD- on J3
J17-J3 thru -6 3 to 5 and 4 to 6: CTS+ on J4-J2 Differential CTS+, CTS- on J3
3 to 4 and 5 to 6: CTS- on J3 or J4
J18-J1 thru -3 1 to 2: 2764, 27128, 27256 EPROMs Must install one or the other
2 to 3: 27512 EPROMs
J19-J1 thru -6 1 to 2 and 4 to 5: 128K x 8 SRAMs Must install one way or the other
2 to 3 and 5 to 6: 32K x 8 SRAMs
J20-J1 thru -3 1 to 2: U2 contains 80C30 or 80230 Must install one way or the other
2 to 3: U2 contains 85C30 or 85230
J21-J1 thru -6 1 to 2 and 4 to 5: U2 contains 80C30 or 80230 Must install one way or the other
2 to 3 and 5 to 6: U2 contains 85C30 or 85230
J22-J1 thru -4 1 to 2: MUSC (USC A) RxREQ on DMA 0
1 to 3: MUSC (USC A) RxREQ on DMA 1
1: MUSC (USC A) Rx no DMA
2 to 4: MUSC (USC A) TxREQ on DMA 0 4: MUSC (USC A) Tx no DMA
3 to 4: MUSC (USC A) TxREQ on DMA 1
J23-J1 thru -3 1 to 2: (E)SCC B RxRQ on DMA 0 (E)SCC B neither Rx DMA
2 to 3: (E)SCC B Wait function nor Wait
J24-J1 thru -4 1 to 2: clipped SCC B TxREQ on DMA 1 (E)SCC B neither Tx DMA
1 to 3: direct ESCC B TxREQ on DMA 1 nor /DTR
3 to 4: /DTR output from ESCC B
J25-J1 thru - 5 and J25X 1 to 2 and 3 to 4: (E)SCC last on IACK chain, Must be one of these three ways
MUSC second to last
J25X to 2 and 3 to 4: (E)SCC last, USC 2nd to last
2 to 3 and 4 to 5: (E)SCC first on IACK chain
J28-J1 thru -6 1 to 2: 80186 SYSCLK is (E)SCC PCLK Connect some other clock to 2, 4, or 6
3 to 4: 80186 SYSCLK is ISCC PCLK
5 to 6: 80186 SYSCLK is IUSC CLK
J29-J1 thru -4 1 to 2: USC B RxREQ on DMA 0
1 to 3: USC B RxREQ on DMA 1
1: USC B Rx no DMA
2 to 4: USC B TxREQ on DMA 0 4: USC B Tx no DMA
3 to 4: USC B TxREQ on DMA 1
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UM011002-0808