Zilog Z16C35 User Manual

Page 33

ISCC

User Manual

UM011002-0808

An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt
Enable bit is set. Note that software may have to test status bits to determine if the channel
interrupt is due to terminal count or an abort.

When the receive DMA enable bit is set, a DMA request is made if the receive FIFO con-
tains a character at the time, or no request will be made until a character enters the receive
FIFO. Note that DMA requests will follow the state of the receive FIFO even though the
receiver is disabled. Thus, if the receiver is disabled and the DMA is still enabled, the
DMA will transfer the previously received data correctly. In this mode the DMA requests
directly follow the state of the receive FIFO. This operation is essentially equivalent to the
DMA requests following the state of the Receive Character Available bit in the SCC cell
in Read Register 0.

The SCC cell will not generate a DMA request in the case of a special receive condition in
the Receive Interrupt on First Character or Special Condition mode, or the Receive Inter-
rupt on Special Condition Only mode.

In these two interrupt modes any receive character with a special receive condition is
locked at the top of the FIFO until an Error Reset command is issued. This character in the
receive FIFO would ordinarily cause additional DMA Requests after the first time it is
read. However, the logic in the SCC cell guarantees no extra DMA transfers by terminat-
ing DMA requests after the time the character with the special receive condition is read,
and the FIFO locked. DMA requests are held off until after the Error Reset command has
been issued.

Once the FIFO is locked, it allows the checking of the Receive Error FIFO (RR1) to find
the cause of the error. Locking the data FIFO therefore, will stop the error status from pop-
ping out of the Receive Error FIFO. Also, since DMA request will become inactive, the
interrupt (Special Condition) can be serviced. Once the FIFO is unlocked by the Error
Reset command, DMA requests again follow the state of the receive FIFO.

Table 3–7. DMA Interrupt Vector Modifications

IV3

IV2

IV1

Interrupt Source

No Interrupt Pending

Not Possible

Rx A Interrupt Pending

Rx B Interrupt Pending

Tx A Interrupt Pending

Tx B Interrupt Pending

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