Zilog Z16C35 - Manual (Page 12)

ISCC
User Manual
UM011002-0808
6
1.3 Pin Description
The following section describes the Z16C35 pin functions. Figures 1-2 and 1-3 detail the
respective pin functions and pin assignments. All references to DMA are internal.
/CTSA, /CTSB. Clear To Send (inputs, active Low). These pins function as transmitter
enables if they are programmed for Auto Enables (WR3, D5). If these pins are pro-
grammed as Auto Enables, a Low on the inputs enables the respective transmitters. If not
programmed as Auto Enables, they may be used as general-purpose inputs. Both inputs
are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC cell detects
transitions on these inputs and can interrupt the CPU on both low to high and high to low
transitions.
/DCDA, /DCDB. Data Carrier Detect (inputs, active Low). These pins function as
receiver enables if they are programmed for Auto Enables (WR3 D5), otherwise they are
used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommo-
date slow rise time signals. The SCC cell detects transitions on these inputs and can inter-
rupt the CPU on both low to high and high to low transitions.
/DTR//REQA, /DTR//REQB. Data Terminal Ready/Request (outputs, active Low).
These pins are programmable (WR14, D2) to serve as either general-purpose outputs or as
DMA request lines. When programmed for the DTR function these outputs follow the
state programmed into the DTR bit of Write Register 5 (WR5, D7). When programmed for
the Ready mode, these pins serve as DMA requests for the transmitter. Note that this DMA
request is not associated with the on-chip DMA and is intended for use in requesting DMA
service from an external DMA.
IEI. Interrupt Enable In (input, active High). IEI is used with IEO to form an interrupt
daisy chain when there is more than one interrupt driven device. A high IEI indicates that
no other higher priority device has an interrupt under service or is requesting an interrupt.
IEO. Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the
CPU is not servicing the ISCC (SCC or DMA) interrupt or the ISCC is not requesting an
interrupt (Interrupt Acknowledge cycle only). IEO is connected to the next lower priority
device’s IEI input and thus inhibits interrupts from lower priority devices.
/INT. Interrupt (output, active Low). This signal is activated when the SCC or DMA
requests an interrupt. Note that /INT is pulled high and is not an open-drain output.
/INTACK. Interrupt Acknowledge (input, active Low). This is a strobe which indicates
that an interrupt acknowledge cycle is in progress. During this cycle, the SCC and DMA
interrupt daisy chain is resolved. The device is capable of returning an interrupt vector that
may be encoded with the type of interrupt pending during this acknowledge cycle when /
RD or /DS become high. /INTACK may be programmed to accept a status acknowledge, a
single pulse acknowledge, or a double pulse acknowledge. This is programmed in the Bus
Page 6 of 316