Zilog Z16C35 - Manual (Page 132)

ISCC
User Manual
UM011002-0808
126
Figure 5–49. Read Register 2
5.5.4 Read Register 3
RR3 is the interrupt Pending register. The status of each of the interrupt Pending bits in the
SCC cell is reported in this register. This register exists only in Channel A. If this register
is accessed in Channel B, all “0’s” are returned. The two unused bits are always returned
as “0”. Figure 5-21 shows the bit positions for RR3.
Figure 5–50. Read Register 3
Read Register 2
D6 D7 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
V4
V5
V6
V7
* Modified in B Channel
Interrupt
Vector *
Read Register 3
D6 D7 D5 D4 D3 D2 D1 D0
Channel B Ext/Status IP
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Status IP
Channel A Tx IP
Channel A Rx IP
0
0
* Always 0 in B Channel
*
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