Zilog Z16C35 - Manual (Page 77)

ISCC
User Manual
UM011002-0808
71
underrun occurs. The frame will be terminated normally, with CRC and a flag, if this bit is
set to “0”, and the Tx Underrun /EOM latch is reset.
The ISCC is also able to send an abort by command of the processor. The Send Abort
command, issued in WR0, will send eight consecutive “1s” and then the transmitter will
idle. The Send Abort command also empties the transmit buffer register. Since up to five
consecutive “1s” may have been sent prior to the Send Abort command being issued, the
command will cause a sequence of from eight to thirteen “1s” to be transmitted (five ones
of data followed by eight ones of the abort).
After the abort when the transmitter enters the idle condition, the ISCC permits sending
continuous 1’s instead of idle flags. This option is invoked by setting the Mark/Flag idle
bit (D3) in WR10 to “1”. Note that the closing flag will be transmitted correctly even if
this mode is selected.
Before a new frame is transmitted, the Mark/Flag idle bit must be set to “0” to allow an
opening flag to be transmitted. The Mark/Flag Idle bit must be set to “0” before data is
written to the transmit buffer. Care must be exercised in doing this because the continuous
“1s” are transmitted, eight at a time (as bytes) by the transmit shift register. After setting
the Mark/Flag Idle bit to “0”, the software must allow time for eight continuous ones to
have left the Transmit Shift register before the first data byte is written to the transmit buf-
fer. This allows the transmitter to recognize that the Flag Idle option has been invoked
then, seeing an empty transmit buffer, the transmitter will load the flag into the shift regis-
ter for transmission. Once the flag load has been done, the data may be placed in the trans-
mit buffer without disturbing the transmission of the flag. (Note that when using the
transmitter in SDLC mode, all data passes through the zero inserter, which adds an extra
five bit times of delay between the Transmit Shift register and the Transmit Data pin.)
The number of bits per transmitted character is controlled by bits D6 and D5 of WR5 and
the way the data is formatted within the transmit buffer. The bits in WR5 allow the option
of five, six, seven, or eight bits per character. When “five bits per character” is selected,
the data must be specially formatted before being written to the transmit buffer. This for-
matting is shown in Table 4-2. In all cases the data must be right-justified, with the unused
bits being programmed as per the table (three zeros to the left of the data followed by 1’s
to the left of the zeros to complete the byte).
An additional bit, carrying parity information, may be automatically appended to every
transmitted character by setting bit D6 of WR4 to “1”. This bit is sent in addition to the
number of bits specified in WR4 or by the data format. The parity sense is selected by bit
D1 of WR4. Parity is not normally used in SDLC mode.
The character length may be changed on the fly, but the desired length must be selected
before the character is loaded into the transmit shift register from the transmit buffer. The
easiest way to ensure this is to write to WR5 to change the character length before writing
the data to the transmit buffer.
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