Zilog Z16C35 - Manual (Page 15)

ISCC
User Manual
UM011002-0808
9
from the addressed location or device, and Write (low) indicating that data is being pre-
sented to the addressed location or device.
/UAS. Upper Address Strobe (Output, active Low). This signal is used if the output
address is more than 16-bit. The upper address, A31-A16, can be latched externally by the
rising edge of this signal. /UAS is active first before /AS becomes active. This signal and /
AS are used by the DMA cell.
/AS. Lower Address Strobe (bidirectional, active Low). When the ISCC is bus master, this
signal is an output, and is used as a lower address strobe for AD15-AD0. It is used in con-
junction with /UAS since the address is 32-bits. This signal and /UAS are used by the
DMA cell when it is bus master. When ISCC is not bus master, this signal is used in the
multiplexed bus modes to latch the address on the AD lines. The /AS signal is not used in
the non-multiplexed bus modes and should be tied to VCC through a resistor in these
cases.
/WAIT//RDY. Wait/Ready (bidirectional, active Low). This signal may be programmed
to function either as a Wait signal or Ready signal during the BCR write. When the BCR is
written to Channel A (A1/A//B High during the BCR write), this signal functions as a /
WAIT and thus supports the READY function of 8X86 microprocessors family. When the
BCR writes to Channel B (A1/A//B Low), this signal functions as a /READY and supports
the /DTACK function of the 680X0 microprocessor family.
This signal is an output when the ISCC in not bus master. In this case, the /Wait//RDY sig-
nal indicates when the data is available during a read cycle; when the device is ready to
receive data during a write cycle; and when a valid vector is available during an interrupt
acknowledge cycle.
When the ISCC is the bus master (the DMA cell has taken control of the bus), the /Wait//
RDY signal functions as a /WAIT or /READY input. Slow memories and peripheral
devices can assert /WAIT to extend /DS during bus transfers. Similarly, memories and
peripherals use /READY to indicate that its output is valid or that it is ready to latch input
data.
/BUSACK. Bus Acknowledge (input, active Low). Signals the bus has been released to
the DMA. If the /BUSACK goes inactive before the DMA transfer is completed, the cur-
rent DMA transfer is aborted.
/BUSREQ. Bus Request (output, active Low). This signal is used by the DMA to obtain
the bus from the CPU.
A0/SCC//DMA. DMA Channel/SCC Select/DMA Select (bidirectional). When this pin is
used as input, a high selects the SCC cell and a low selects the DMA cell, (during BCR
Write should be kept Low). When this pin is used as output, the signal on this pin is used
in conjunction with A1/A//B pin output to identify which DMA channel is active. This
information can be used by the user to determine whether to issue a DMA abort command.
A0/SCC//DMA and A1/A//B output encoding is shown on the following page.
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