Zilog Z16C35 - Manual (Page 108)

ISCC
User Manual
UM011002-0808
102
transmitter is in Monosync mode using the contents of WR6 as the time fill with the sync
character length specified by the 6-bit/8-bit Sync bit in WR10.
Bits 3 and 2 are the Stop Bits selection, Bits 1 and 0
These bits determine the number of stop bits added to each asynchronous character that is
transmitted. The receiver always checks for one stop bit in Asynchronous mode. A Special
mode specifies that a Synchronous mode is to be selected. D2 is always set to “1” by a
channel or hardware reset to ensure that the /SYNC pin is in a known state after a reset.
Bit combination 00 selects Synchronous Modes Enable. This bit combination selects one
of the synchronous modes specified by bits D4, D5, D6, and D7 of this register and forces
the 1X Clock mode internally.
Bit combination 01 selects 1 Stop Bit/Character. This bit combination selects Asynchro-
nous mode with one stop bit per character.
Bit combination 10 selects 1 1/2 Stop Bits/Character. These bits select Asynchronous
mode with 1-1/2 stop bits per character. This mode can not be used with the 1X clock
mode.
Bit combination 11 selects 2 Stop Bits/Character. These bits select Asynchronous mode
with two stop bits per transmitted character and check for one received stop bit.
Bit 1 is the Parity Even//Odd select bit
This bit determines whether parity is checked as an even or odd. A “1” programmed here
selects even parity, and a “0” selects odd parity. This bit is ignored if the Parity enable bit
is not set.
Bit 0 is the Parity Enable
When this bit is set, an additional bit position beyond those specified in the bits/character
control is added to the transmitted data and is expected in the receive data. The Received
Parity bit is transferred to the CPU as part of the data unless eight bits per character is
selected in the receiver.
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