Zilog Z16C35 User Manual

Page 85

ISCC

User Manual

UM011002-0808

“0” is received, either by itself or as the leading “0” of a flag. The receiver does not leave
Hunt mode until a flag has been received so two discrete external/status conditions will
occur at the end of an abort. An abort received in the middle of a frame terminates the
frame reception, but not in an orderly manner, because the character being assembled is
lost.

Up to two modem control signals associated with the receiver are available in SDLC
mode:

The /DTR//REQ pin carries inverted state of the DTR bit (D7) in WR5 unless this pin has
been programmed to carry a DMA Request signal.

The /DCD pin is ordinarily a simple input to the DCD bit in RR0. However, if the Auto
Enables mode is selected by setting bit D5 of WR3 to “1”, this pin becomes an enable for
the receiver. That is, if Auto Enable is on and the /DCD pin is High the receiver is dis-
abled. While the /DCD pin is Low, the receiver is enabled.

The initialization sequence for the receiver in SDLC mode is WR4 first, to select the
mode, then WR10 to modify it if necessary, WR6 to program the address, WR7 to pro-
gram the flag and WR3 and WR5 to select the various options. At this point the other reg-
isters should be initialized as necessary. When all of this is completed the receiver may be
enabled by setting bit 0 of WR3 to a one. A summary is shown in Table 4-13.

Initializing the Receiver in SDLC Mode

Table 4–21. Initializing the Receiver in SDLC Mode

Register

Bit No

Description

WR3

6-7

Number of bits per character

WR4

0-1

Select parity

WR5

Select CRC-CCITT Generator

WR10

Select CRC preset value

5-6

Select NRZ/NRZI encoding

WR5

DTR/REQ

WR6

0-7

Address

WR7

0-7

Flag

WR3

Auto enable

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