Zilog Z16C35 - Manual (Page 206)

Application Note
The Z180™ Interfaced with the SCC at MHZ
7
call initdma
ld b,0 ;init status
ld a,00h ;load 1st data to be sent
out (scc_data),a
ld a,11001100b ;enable dmac and int from DMA0
out0 (dstat),a
ld a,05h ;select WR5
out (scc_cont),a
ld a,01101000b ;start tx
out (scc_cont),a
ei ;wait here for completion
loop: bit 1,b ;rx dma end?
jr z,loop ;not, then loop again
push bc ;save bc reg
ld bc,length ;compare tx data with rx data
ld de,tx_buff
ld hl,rx_buff
chkloop: ld a,(de)
cpi
jr
nz,bad_data
jp v,good
inc de
jr chkloop
bad_data: pop bc ;restore bc
set 2,b ;set error flag
jr enddma
good: pop bc ;restore bc
enddma: jr $ ;tx/rx completed
; you can put breakpoint here
fill_mem: l d hl,temp ; prepare data to be sent
ld bc,length ; set length
ld de,tx_buff
ld (hl),00h
fill_loop: ldi
jp
nv,fill_00
dec hl
inc (hl)
jr fill_loop
fill_00: ld bc,length ; clear rx buffer area to zero
ld de,rx_buff
ld (hl),00h
fill_00l: ldi
ret
nv
dec hl
jr fill_00l
Table 14. Test Program – Z180/SCC DMA Transfer (Continued)
Page 200 of 316
UM011002-0808