Zilog Z16C35 - Manual (Page 63)

ISCC
User Manual
UM011002-0808
57
In character-oriented modes, a special bit pattern is used to provide character synchroniza-
tion. The ISCC offers several options to support synchronous mode including various sync
generation and checking, CRC generation and checking, as well as modem controls and a
transmitter to receiver synchronization function.
For a 16-bit sync character, set bit D4 of WR4 to “1” and bit D5 of WR4 and bit D0 of
WR10 to “0”. In this mode the transmitter sends the concatenation of WR6 and WR7 as a
time fill.
Because the receiver requires that sync characters be left-justified in the registers, while
the transmitter requires them to be right justified, only the receiver will work with a 12-bit
sync character. While the receiver is in External Sync mode, the transmitter sync length
may be six or eight bits, as selected by bit D0 of WR10.
The number of bits per transmitted character is controlled by D6 and D5 of WR5 and the
way the data is formatted within the transmit buffer. The bits in WR5 allow the option of
five, six, seven, or eight bits per character. When five bits per character is selected the data
may be formatted before being written to the transmit buffer to allow transmission of from
one to five bits per character. This formatting is shown in Table 4-2. In all cases the data
must be right-justified, with the unused bits being ignored except in the case of five bits
per character.
An additional bit, carrying parity information, may be automatically appended to every
transmitted character by setting bit D0 of WR4 to “1”. This parity bit is sent in addition to
the number of bits specified in WR4 or by the data format. If this bit is set to “1”, the
transmitter will send even parity, if set to “0”, the transmitted parity will be odd.
Either of two CRC polynomials may be used in synchronous modes, selected by bit D2 in
WR5. If this bit is set to “1”, the CRC-16 polynomial is used and, if this bit is set to “0”,
the CRC-CCITT polynomial is used. This bit controls the selection for both the transmitter
and receiver. The initial state of the generator and checker is controlled by bit D7 of
WR10. When this bit is set to “1”, both the generator and checker will have an initial value
of all ones, if this bit is set to “0”, the initial values will be all zeros.
The ISCC does not automatically preset the CRC generator, so this must be done in soft-
ware. This is accomplished by issuing the Reset Tx CRC Generator command, which is
encoded in bits D7 and D6 of WR0. For proper results this command must be issued while
the transmitter is enabled and sending sync characters.
If CRC is to be used, the transmit CRC generator must be enabled by setting bit D0 of
WR5 to “1”. This bit may also be used to exclude certain characters from the CRC calcu-
lation. Sync characters are automatically excluded from the CRC calculation and any
characters written as data may also be excluded from the calculation by using bit D0 of
WR5. Internally, the CRC is enabled or disabled for a particular character at the same time
as the character is loaded from the transmit buffer to the Transmit Shift register. Thus, to
exclude a character from CRC calculation bit D0 of WR5 should be set to “0” before the
character is written to the transmit buffer. This guarantees that the internal disable will
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