Zilog Z16C35 User Manual
Page 160
Application Note
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
6-6
INPUT/OUTPUT CYCLES
(Continued)
.
Table 2. Z8500 Timing Parameters I/O Cycles
Worst Case
Min
Max
Units
6.
TsA(WR)
Address to /WR to Low Setup
80
ns
1.
TsA(RD)
Address to /RD Low Setup
80
ns
2.
TdA(DR)
Address to Read Data Valid
590
TsCEI(WR)
/CE Low to /WR Low Setup
ns
TsCEI(RD)
/CE Low to /RD Low Setup
ns
4.
TwRDI
/RD Low Width
390
ns
8.
TwWRI
/WR Low Width
390
ns
3.
TdRDf(DR)
/RD Low to Read Data Valid
255
ns
7.
TsDW(WR)
Write Data to /WR Low Setup
0
ns
Table 3. Z80A Timing Parameters I/O Cycles
Worst Case
Min
Max
Units
TcC
Clock Cycle Period
250
ns
TwCh
Clock Cycle High Width
110
ns
TfC
Clock Cycle Fall Time
30
ns
TdCr(A)
Clock High to Address Valid
110
ns
TdCr(RDf)
Clock High to /RD Low
85
ns
TdCr(IORQf)
Clock High to /IORQ Low
75
ns
TdCr(WRf)
Clock High to /WR Low
65
ns
5.
TsD(Cf)
Data to Clock Low Setup
50
ns
Table 4. Parameter Equations
Z8500
Parameter
Z80A
Equation
Value
Units
TsA(RD)
TcC-TdCr(A)
140 min
ns
TdA(DR)
3TcC+TwCh-TdCr(A)-TsD(Cf)
800 min
ns
TdRDf(DR)
2TcC+TwCh-TsD(Cf)
460 min
ns
TwRD1
2TcC+TwCh+TfC-TdCr(RDf)
525 min
ns
TsA(WR)
TcC-TdCr (A)
140 min
ns
TsDW(WR)
>0 min
ns
TwWR1
2TcC+TwCh+TfC-TdCr(WRf)
560 min
ns
Table 5. Parameter Equations
Z80A
Parameter
Z8500
Equation
Value
Units
TsD(Cf)
3TcC+TwCh-TdCr(A)-TdA(DR)
160 min
ns
/RD
2TcC+TwCh-TdCr(RDf)-TdRD(DR)
135 min
ns
Page 154 of 316
UM011002-0808