Zilog Z16C35 - Manual (Page 40)

ISCC
User Manual
UM011002-0808
34
The first command selects the baud rate generator as the clock source. The other command
selects /RTxC pin as the clock source, independent of whether the /RTxC pin is a simple
input or part of the crystal oscillator circuit.
Initialization of the DPLL may be done at any time during the initialization sequence, but
should preferably be done after the clock modes have been selected in WR11, and before
the receiver and transmitter are enabled. When initializing the DPLL, the clock source
should be selected first, followed by the selection of the operating mode.
To avoid metastable problems in the counter, the clock source selection should be made
only while DPLL is disabled, since arbitrarily narrow pulses can be generated at the output
of the multiplexer when it changes status.
The DPLL is enabled by issuing the Enter Search Mode command in WR14; that is WR14
(7-5) = 001. The Enter Search Mode command unlocks the counter, which is held while
the DPLL is disabled, and enables the edge detector. If the DPLL is already enabled when
this command is issued, the DPLL also enters Search Mode.
Enter Search Mode is also used to reset the DPLL to a known state if it is suspected that
synchronization has been lost. Note that the DPLL and the receiver are independent, so
whether the receiver is disabled or not enabled, DPLL will sample whatever is on the RxD
line.
DPLL requires a transition in every bit cell, and if this transition is not present in two con-
secutively sampled bit cells, the DPLL will automatically enter search mode and the
DPLL will not provide any clock output.
In Search mode, the counter is held at a specific count and no outputs are provided. The
DPLL remains in this status until an edge is detected in the receive data stream. This first
edge is assumed to occur on a bit cell boundary, and the DPLL will begin providing an
output to the receiver that will properly sample the data. From this point on the DPLL will
adjust its output to remain in phase with the receive da-ta. If the first edge that the DPLL
sees does not occur on a bit cell boundary, the DPLL will eventually lock on to the receive
data, but it will take longer to do so.
The DPLL may be programmed to operate in either of two modes, as selected by com-
mand in WR14.
WR14 (7-5) = 111 for NRZI mode and
WR14 (7-5) = 110 for FM mode
Note that a channel or hardware reset disables the DPLL, selects the /RTxC pin as the
clock source for the DPLL, and places it in the NRZI mode.
As in the case of the clock source selection, the mode of operation should only be changed
while the DPLL is disabled to prevent unpredictable results.
In the NRZI mode, the DPLL clock must be 32 times the data rate. In this mode, the trans-
mit and receive clock outputs of the DPLL are identical, and the clocks are phased so that
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