Zilog Z16C35 - Manual (Page 18)

ISCC
User Manual
UM011002-0808
12
ter (CSAR bits 4 - 0). The SCC cell and DMA cell pointers are independent. Detailed
operation is described in a later section.
2.2.2 Multiplexed Bus Operation
When the ISCC is initialized for multiplexed bus operation, all registers in the SCC cell
are directly addressable with the register address occupying AD5 through AD1, or AD4
through AD0 (Shift Left/Shift Right modes). The A0/SCC //DMA pin controls the SCC
cell /DMA selection. The SCC cell channel A/B selection may be controlled either by the
A0/A//B pin or by the A/B selection in the address on AD7-AD0 that is strobed into the
ISCC with /AS. Use of this re-quires that the unused SCC channel select option to be set to
Channel A. That is, if the A0/A//B pin is used to select the channel, then the AD bit for
channel selection must select channel A (the actual bit is determined by the Shift Left/
Shift Right mode employed) and conversely, if the AD bus bit is used to select the chan-
nel, then the A0/A//B pin must select channel A. Refer to the A0/SCC//DMA and A1/A//B
pin descriptions for the encoding of these signals.
In the multiplexed bus mode of operation, the register pointer in WR0 of the SCC cell is
ignored and has no effect on the accessing of the internal registers. Register access is made
solely through the latched address. However, the pointer in the DMA Channel Command/
Address Register functions in the multiplexed bus mode and may be used to access DMA
registers in a manner identical to that in the non-multiplexed bus mode. To use the DMA
pointer in the multiplexed bus mode, the multiplexed address must always address the
CCAR of the DMA even though the actual register access will be made according to the
pointer. This requires that in the normal multiplexed mode of operation with register
access through the latched address, writes to the DMA CCAR must always write zeros to
the pointer field.
In the multiplexed bus mode in some host configurations, address A0 may be used for byte
transfer control in 16-bit systems. Therefore, it may be necessary to ignore A0 in the regis-
ter decode. This is accommodated in the ISCC by providing an option to decode the multi-
plexed address from A1 upwards rather than from A0 upwards. This option is the Shift
Left/Shift Right mode. The Shift Left/Shift Right modes for the address decoding for the
internal registers (multiplexed bus) are separately programmable for the SCC cell and for
the DMA cell. For the SCC cell the programming and operation is identical to that in the
SCC; programming is accomplished through Write Register 0 (WR0), bits 1 and 0 (Figure
5-2). The programming of the Shift Left/Shift Right modes for the DMA cell is accom-
plished in the BCR, bit 0. In this case, the shift function is similar to that for the SCC cell;
with Shift left, the internal register addresses are decoded from bits AD5 through AD1 and
with Shift Right, the internal register addresses are decoded from bits AD4 through AD0.
When the multiplexed bus mode is selected, Write Register 0 (WR0) takes on the form of
WR0 in the Z8030 (Figure 5-2).
Page 12 of 316