Zilog Z16C35 - Manual (Page 128)

ISCC
User Manual
UM011002-0808
122
been lost or that a new message is about to start. Both transitions on the /SYNC pin cause
External/Status interrupts if the Sync/Hunt IE bit is set to “1”.
The Enter Hunt Mode command should be issued whenever character synchronization is
lost. At the same time, the CPU should inform the external logic that character synchroni-
zation has been lost and that the ISCC is waiting for /SYNC to become active.
In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to “1”
by the Enter Hunt Mode command. The Sync/Hunt bit is reset when the ISCC established
character synchronization. Both transitions cause External/Status interrupts if the Sync/
Hunt IE bit is set. When the CPU detects the end of message or the loss of character syn-
chronization, the Enter Hunt Mode command should be issued to set the Sync/Hunt bit
and cause an External/Status interrupt. In this mode, the SYNC pin is an output, which
goes Low every time a sync pattern is detected in the data stream.
In the SDLC modes, the Sync/Hunt bit is initially set by the Enter Hunt Mode command or
when the receiver is disabled. It is reset when the opening flag of the first frame is detected
by the ISCC. An External/Status interrupt is also generated if the Sync/Hunt IE bit is set.
Unlike the Monosync and Bisync modes, once the Sync/Hunt bit is reset in SDLC mode, it
does not need to be set when the end of the frame is detected. The ISCC automatically
maintains synchronization. The only way the Sync/Hunt bit can be set again is by the
Enter Hunt Mode command or by disabling the receiver.
Bit 3 is the Data Carrier Detect status
If the DCD IE bit in WR15 is set, this bit indicates the state of the DCD pin the last time
the Enabled External/Status bits changed. Any transition on the DCD pin while no inter-
rupt is pending latches the state of the DCD pin and generates an External/Status interrupt.
Any odd number of transitions on the DCD pin while another External/Status interrupt is
pending will also cause an External/Status interrupt condition. If the DCD IE is reset, this
bit merely reports the current, unlatched state of the DCD pin.
Bit 2 is the TX Buffer Empty status
This bit is set to “1” when the transmit buffer is empty. It is reset while CRC is sent in a
synchronous or SDLC mode and while the transmit buffer is full. The bit is reset when a
character is loaded into the transmit buffer. This bit is always in the set condition after a
hardware or channel reset.
Bit 1 is the Zero Count status
If the Zero Count interrupt Enable bit is set in WR15, this bit is set to one while the coun-
ter in the baud rate generator is at the count of zero. If there is no other External/Status
interrupt condition pending at the time this bit is set, an External/Status interrupt is gener-
ated. However, if there is another External/Status interrupt pending at this time, no inter-
rupt is initiated until interrupt service is complete. If the Zero Count condition does not
persist beyond the end of the interrupt service routine, no interrupt will be generated. This
bit is not latched High, even thought the other External/Status latches close as a result of
the Low-to-High transition on Zero Count. The interrupt routine should check the other
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