Zilog Z16C35 - Manual (Page 64)

ISCC
User Manual
UM011002-0808
58
occur when the character moves from the buffer to the shift register. Once the buffer
becomes empty, the Tx CRC Enable bit may be written for the next character.
Enabling the CRC generator is not sufficient to control the transmission of CRC. In the
ISCC this function is controlled by the Tx Underrun/EOM bit, which may be reset by the
processor and set by the ISCC. When the transmitter underruns (both the transmit buffer
and Transmit Shift register are empty) the state of the Tx Underrun/EOM bit determines
the action taken by the ISCC. If the Tx Underrun/EOM bit is not set when the underrun
occurs, the transmitter will send the accumulated CRC and set the Tx Underrun/EOM bit
to indicate this. This transition may be programmed to cause an external/status interrupt,
or the Tx Underrun/EOM is available in RR0.
The Reset Tx Underrun/EOM Latch command is encoded in bits D7 and D6 of WR0. For
correct transmission of the CRC at the end of a block of data, this command must be
issued after the first character is written to the ISCC but before the transmitter underruns
after the last character written to the ISCC. The command is usually issued immediately
after the first character is written to the ISCC so that CRC will be sent if an underrun
occurs inadvertently during the block of data.
If the transmitter is disabled during transmission of a character, that character will be sent
completely. This applies to both data and sync characters. However, if the transmitter is
disabled during the transmission of CRC, the 16-bit transmission will be completed, but
the remaining bits will come from the SYNC registers rather than the remainder of the
CRC.
There are two modem control signals associated with the transmitter provided by the
ISCC: /RTS and /CTS.
The /RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5.
The /CTS pin is ordinarily a simple input to the CTS bit in RR0. However, if Auto Enables
mode is selected this pin becomes an enable for the transmitter. That is, if Auto Enables is
ON and the /CTS pin is High the transmitter is disabled. While the /CTS pin is Low, trans-
mitter is enabled.
The initialization sequence for the transmitter in character-oriented mode is shown in
Table 4-6.
Table 4–14. Transmitter Initialization in Character Oriented Mode
Register Bit No Description
WR4 0,1 select parity
WR5 1 RTS
2 select CRC generator
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