Zilog Z16C35 - Manual (Page 13)

ISCC
User Manual
UM011002-0808
7
Configuration Register (BCR). The double pulse acknowledge is compatible with 8X86
family microprocessors.
PCLK. Clock (input). This is the master SCC cell and DMA cell clock used to synchro-
nize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase
relationship with the master system clock.
RxDA, RxDB. Receive Data (inputs, active High). These input signals receive serial data
at standard TTL levels.
/RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, active Low). These pins can be pro-
grammed to several modes of operation. In each channel, /RTxC may supply the receive
clock, the transmit clock, the clock for the baud rate generator, or the clock for the Digital
Phase-Locked Loop. These pins can also be programmed for use with the respective /
SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data
rate in asynchronous modes.
/RTSA, /RTSB. Request To Send (outputs, active Low). When the Request To Send
(RTS) bit in Write Register 5 is set, the /RTS signal goes Low. When the RTS bit is reset in
the Asynchronous mode and Auto Enable is on, the signal goes High after the transmitter
is empty. In Synchronous mode or in Asynchronous mode with Auto Enable off, the /RTS
pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose out-
puts.
/SYNCA, /SYNCB. Synchronization (inputs or outputs, active Low). These pins can act
either as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous
Receive mode (crystal oscillator option not selected), these pins are inputs similar to /CTS
and /DCD. In this mode, transitions on these lines affect the state of the Sync/Hunt status
bits in Read Register 0 but have no other function.
In External Synchronization mode with the crystal oscillator not selected, these lines also
act as inputs. In this mode, /SYNC must be driven Low two receive clock cycles after the
last bit in the synchronous character is received. Character assembly begins on the rising
edge of the receive clock immediately preceding the activation of /SYNC.
In the Internal Synchronization mode (Monosync and Bi-sync) with the crystal oscillator
not selected, these pins act as outputs and are active only during the part of the receive
clock cycle in which sync condition is not latched. These outputs are active each time a
sync pattern is recognized (regardless of character boundaries). In SDLC mode, the pins
act as outputs and are valid on receipt of a flag. The output is active for one receive clock
period (refer to Chapter 4).
TxDA, TxDB. Transmit Data (outputs, active high). These output signals transmit serial
data at standard TTL levels.
/TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or outputs, active Low). These pins
can be programmed in several different modes of operation. /TRxC may supply the
receive clock or the transmit clock in the input mode or supply the output of the Digital
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