Zilog Z16C35 - Manual (Page 84)

ISCC
User Manual
UM011002-0808
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set value. If this bit is set to “1”, the generator and checker are preset to “1s”, if this bit is
reset, the generator and checker are present to all “0s”.
The receiver expects the CRC to be inverted before trans-mission and so checks the CRC
result against the value “0001110100001111”. The ISCC presets the CRC checker when-
ever the receiver is in Hunt mode or whenever a flag is received so a CRC reset command
is not strictly necessary. However, the CRC checker may be preset by issuing the Reset
CRC Checker command in WR0.
The CRC checker is automatically enabled for all data between the opening and closing
flags by the SCC cell in SDLC mode, and the Rx CRC Enable bit (D3) in WR3 is ignored.
The result of the CRC calculation for the entire frame is valid in RR1 only when accompa-
nied by the End of Frame bit being set in RR1. At all other times the CRC Error bit in RR1
should be ignored by the processor.
Care must be exercised so that the processor does not attempt to use the CRC bytes that
are transferred as data because not all of the bits are transferred properly. The last two bits
of CRC are never transferred to the receive data FIFO and are not recoverable.
Note the following about ISCC CRC operation:
The normal CRC checking mechanism involves checking over data and CRC characters.
If the division remainder is 0, there is no CRC error.
SDLC is different. The CRC generator, when receiving a correct frame, will have a fixed,
non-zero remainder. The actual remainder in the receive CRC calculation must be checked
against this fixed value to determine if a CRC error exists.
A frame is terminated by a closing flag. When the ISCC recognizes this flag:
The contents of the Receive Shift register are transferred to the receive data FIFO.
The Residue Code is latched, and the CRC Error bit is latched in the status FIFO and the
End of Frame bit is set in the receive status FIFO.
The End of Frame bit, upon reaching the top of the FIFO, will cause a special receive con-
dition. The processor may then read RR1 to determine the result of the CRC calculation as
well as the Residue Code. If either the Rx Interrupt or Special Condition Only or the Rx
Interrupt on First Character or Special Condition modes are selected, the FIFO will be
locked, and the processor must issue an Error Reset command in WR0 to unlock the
receive FIFO.
In addition to searching the data stream for flags, the receiver in the ISCC also watches for
seven consecutive “1s”, which is the abort condition. The presence of seven consecutive
“1s” is reported in the Break/Abort bit in RR0. This is one of the possible external/status
interrupts, so transitions of this status may be programmed to cause interrupts. Upon
receipt of an abort the receiver is forced into Hunt mode where it looks for flags. The Hunt
status is also a possible external/status condition whose transition may be programmed to
cause an interrupt. The transitions of these two bits occur very close together but either
one or two external/status interrupts may result. The abort condition is terminated when a
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