Zilog Z16C35 - Manual (Page 60)

ISCC
User Manual
UM011002-0808
54
the data FIFO. The three error conditions that the receiver checks for in asynchronous
mode are:
1. Framing errors - when a character stop bit is found to be 0.
2. Parity errors - when parity is enabled and the parity of a character disagrees with the
sense programmed in WR4.
3. Overrun errors - when the FIFO overflows.
The initialization sequence for the receiver in asynchronous mode is given in Table 4-4
below.
Table 4-4. Initialization Sequence for the Receiver in Asynchronous Mode
At this point other registers should be initialized according to the hardware design such as
clocking, I/O mode, etc. When all this is completed, the receiver may be enabled by set-
ting WR3(0) = 1. Also note that the transmitter and receiver may be initialized at the same
time.
4.3 BYTE-ORIENTED SYNCHRONOUS MODE
Three byte-oriented synchronous protocols supported by ISCC are monosync, bisync, and
external sync.
In synchronous communications the bit cell boundaries are defined by a clock signal
which is common to both the transmitter and receiver. Of course there must also be an
agreement as to the location of the character boundaries so that the characters can be prop-
erly framed. This is normally accomplished by defining special SYNC patterns, or SYNC
characters. The SYNC pattern serves as a reference; it signals the receiver that a character
boundary occurs immediately after the last bit of the pattern. Another way of identifying
Table 4–12. Initialization Sequences for the Receiver in Asynchronous Mode
Reg Bit No Description
WR4 3, 2 Select Async Mode and the number of stop bits*
0, 1 Select parity*
6, 7 Select clock mode*
WR3 7, 6 Select number of bits/character
5 Select Auto Enable Mode*
WR5 1 Select modem control (RTS)
Note: * Initializes transmitter and receiver simultaneously
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