Zilog Z16C35 - Manual (Page 17)

ISCC
User Manual
UM011002-0808
11
Chapter 2 Interfacing the ISCC™
2.1 Introduction
This chapter details the interfacing of the 16C35 ISCC to a system. Covered in this chapter
is a description of the Bus Interface Unit (BIU) and information about the ISCC in non-
multiplexed and multiplexed bus operation. The following section entails the ISCC’s
capabilities for three types of I/O operations: polling, interrupt (vectored or non-vectored),
and DMA Transfer modes. Also included in this chapter is information about the ISCC
registers and register access.
2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION
The ISCC™ contains a flexible bus interface that is compatible with a variety of micro-
processors and microcontrollers. The device is designed to work with 8- or 16-bit bus sys-
tems and may be used with address/data multiplexed buses or non-multiplexed buses. The
bus interface style is selected by certain actions which take place after a hardware reset.
The ISCC contains a Bus Configuration Register, the BCR. This register has no address
and is only accessible in the first transaction to the ISCC after a hardware reset; this first
transaction must be a write with AØ/sec//DMA Low and is automatically directed to the
Bus Configuration Register by the ISCC. The Bus Configuration Register contains bits
which program the byte swapping feature, the interrupt acknowledge type and other
aspects of the bus interface configuration. Refer to Chapter 5 for BCR details.
The multiplexed bus is selected for the ISCC if there is an Address Strobe prior to or dur-
ing the transaction which writes the BCR. If no Address Strobe is present prior to or dur-
ing the transaction which writes the BCR, a non-multiplexed bus is selected. The address
strobe is recognized whether or not the ISCC Chip Enable is active.
2.2.1 Non-Multiplexed Bus Operation
When the ISCC is initialized for non-multiplexed operation, register addressing for the
ISCC cell is (with the ex-ception of WR0 and RR0), accomplished using an internal
pointer accessed via WR0. Accessing internal registers by this means is a two step opera-
tion requiring a write to the pointer followed by access of the desired register. This is
described in detail in later sections. Note that when the DMA is not used to address the
data, the data registers must be accessed by pointing to Register 8. (This is in contrast to
the Z8530 which allows direct addressing of the data registers through the C/D pin.)
When the ISCC is initialized for non-multiplexed operation, register addressing for the
DMA cell (with the exception of CSAR) is accomplished in a manner similar to that used
in the SCC cell. In this case the pointer is accessed in the Command Status Address Regis-
Page 11 of 316