Zilog Z16C35 - Manual (Page 123)

ISCC
User Manual
UM011002-0808
117
first data edge. Beyond this point, the DPLL begins normal operation, adjusting the output
to remain in sync with the incoming data.
In FM mode, the output of the DPLL is Low while the DPLL is waiting for an edge in the
incoming data stream. The first edge the DPLL detects is assumed to be a valid clock
edge. For this to be the case, the line must contain only clock edges; i.e., with FM1 encod-
ing, the line must be continuous “0s.” With FM0 encoding the line must be continuous
“1s,” whereas Manchester encoding requires alternating “1s” and “0s” on the line. The
DPLL clock rate must be 16 times the data rate in FM mode. The DPLL output causes the
receiver to sample the data stream in the nominal center of the two halves of the bit cell to
decide whether the data was a “1” or a “0.” After this command is issued, as in NRZI
mode, the DPLL starts sampling immediately after the first edge is detected. (In FM mode,
the DPLL examines the clock edge of every other bit cell to decide what correction must
be made to remain in sync.) If the DPLL does not see an edge during the expected win-
dow, the one clock missing bit in RR10 is set. If the DPLL does not see an edge after two
successive attempts, the two clocks missing bit in RR10 is set and the DPLL automatically
enters the Search mode. This command resets both clock missing latches.
Bit combination 010 is the Reset Clock Missing Command. Issuing this command dis-
ables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search
mode state.
Bit combination 001 is the Disable DPLL Command. Issuing this command disables the
DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode
state.
Bit combination 100 is the Set Source = BR Gen Command. Issuing this command forces
the clock for the DPLL to come from the output of the baud rate generator.
Bit combination 101 is the Set Source = /RTxC Command. Issuing the command forces
the clock for the DPLL to come from the /RTxC pin or the crystal oscillator, depending on
the state of the XTAL/NO XTAL bit in WR11. This mode is selected by a channel or hard-
ware reset.
Bit combination 110 is the Set FM Mode Command. This command forces the DPLL to
operate in the FM mode and is used to recover the clock from FM or Manchester-encoded
data. (Manchester is decoded by placing the receiver in NRZ mode while the DPLL is in
FM mode.)
Bit combination 111 is the Set NRZI Mode Command. Issuing this command forces the
DPLL to operate in the NRZI mode. This mode is also selected by a hardware or channel
reset.
Bit 4 is the Local Loopback select bit
Setting this bit to “1” selects the Local Loopback mode of operation. In this mode, the
internal transmitted data is routed back to the receiver, as well as to the TxD pin. The /CTS
and /DCD inputs are ignored as enables in Local Loopback mode, even if auto enables is
selected. (If so programmed, transitions on these inputs still cause interrupts.) This mode
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