Zilog Z16C35 - Manual (Page 21)

ISCC
User Manual
UM011002-0808
15
the contents of the register, the CPU either reads data, writes data, or satisfies an error con-
dition. Two bits in the register indicate the need for data transfer. An alternative is to poll
the Interrupt Pending register to determine the source of an interrupt. The status for both
SCC channels resides in one register.
2.3.2 Interrupts
When the ISCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU,
an interrupt vector is placed on the data bus. Both the SCC and the DMA contain vector
registers. Depending on the source of interrupt, one of these vectors is returned, either
unmodified or modified by the interrupt status to indicate the exact cause of the interrupt.
Each of the six sources of interrupt in the SCC (Transmit, Receive, and External/Status
interrupts in both channels) and each DMA channel has three bits associated with interrupt
source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). If
the IE bit is set for any given source of interrupt, then that source can request interrupts.
The only exception to this rule is when the associate Master Interrupt Enable (MIE) bit is
reset, then no interrupts are requested. Both the SCC cell and the DMA have an associated
MIE bit. The IE bits in the SCC cell are write only, but the IE bits in the DMA are read/
write.
The ISCC provides for nesting of interrupt sources with an interrupt daisy chain using the
IEI, IEO, and /INTACK pins. As a microprocessor peripheral, the ISCC may request an
interrupt only when no higher priority device is requesting one, e.g., when IEI is High. If
the device in question requests an interrupt, it enables the /INT signal. The CPU then
responds with /INTACK, and the interrupting cell places the vector on the data bus.
In the ISCC, the IP bit signals a need for interrupt servicing. When an IP bit is 1 and the
IEI input pin is High, the /INT signal is activated, requesting an interrupt. In the SCC cell,
if the IE bit is not set, then the IP for that source can never be set. The IP bits in the DMA
cell are set independent of the IE bit.
The IUS bits signal that an interrupt request is being ser-viced. If an IUS is set, all inter-
rupt sources of lower priority in the ISCC and external to the ISCC are prevented from
requesting interrupts. The internal interrupt sources are inhibited by the state of the inter-
nal daisy chain, while lower priority devices are inhibited by the IEO output of the ISCC
being pulled Low and propagated to subsequent peripherals. Internally, the SCC cell is
higher priority than the DMA cell. An IUS bit is set during an Interrupt Acknowledge
cycle if there are no higher priority devices requesting interrupts. The IUS bit must be
cleared by the CPU. This is usually done at the end of the correspond-ing interrupt service
routine.
Within the SCC portion of the ISCC there are three types of interrupts: Transmit, Receive,
and External/Status. Each interrupt type is enabled under program control with Channel A
having higher priority than Channel B, and with Receive, Transmit, and External/Status
interrupts prioritized in that order within each channel. When the Transmit interrupt is
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