Zilog Z16C35 - Manual (Page 172)

Application Note
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
6-18
EXTERNAL INTERFACE LOGIC (Continued)
During RETI cycles, the IEO line from the Z8500 peripherals
does not change state as in the Z80 peripherals. As long as
the peripherals are at the top of the daisy chain, propagation
delays are minimized. The logic necessary to create the control signals for both
Z80 and Z8500 peripherals is shown in Figure 9. This logic
delays the generation of /IORQ to the Z80 peripherals by
the same amount of time necessary to generate /READ for
the Z8500 peripherals. Timing for this logic during an
Interrupt Acknowledge cycle is depicted in Figure 10.
Figure 11. Z80H to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic
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