Zilog Z16C35 User Manual
Page 9
ISCC
User Manual
UM011002-0808
3
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Independent DMA Register Set
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A Universal Bus Interface Unit Providing Simple Interface to Most CPUs Multiplexed
or Non-Multiplexed Bus; Compatible with 680X0 and 8X86 CPUs
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32-Bit Addresses Multiplexed to 16-pin Address/Data Lines
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8-Bit Data Supporting High/Low Byte Swapping
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10 MHz Timing
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12.5 and 16 MHz Timing Planned
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68-Pin PLCC
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Supports all Zilog CMOS SCC Features:
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Two Independent, 0 to 4.0 Mbit/Second, Full-Duplex Channels, Each with a Separate
Crystal Oscillator, Baud Rate Generator, and Digital Phase-Locked Loop Circuit for
Clock Recovery.
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Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or
FM Data Encoding.
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Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop
Bits per Character; Programmable Clock Factor; Break Detection and Generation; Par-
ity, Overrun, and Framing Error Detection.
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Synchronous Mode with Internal or External Character Synchronization on One or
Two Synchronous Characters and CRC Generation and Checking with CRC-16 or
CRC-CCITT preset to either 1’s or 0’s.
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SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Inser-
tion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC
Generation and Checking, and SDLC Loop Mode Operation.
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Local Loopback and Auto Echo modes
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Supports T1 Digital Trunk
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Enhanced SDLC 10x19 Status FIFO for DMA Support
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Full CMOS SCC Register Set
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